Buffer Insertion in Dataflow Graphs via Backedge Removal
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Solution Overview
Problem
Existing methods for balancing latency in dataflow graphs, particularly in coarse-grained reconfigurable architectures, fail to effectively manage latency across critical and noncritical paths, leading to suboptimal data processing throughput due to the presence of backedges and inadequate buffer insertion techniques.
Innovation Solution
The implementation of a compiler workflow that includes backedge detection and removal, followed by buffer insertion in noncritical paths to balance latency, using techniques such as depth-first search, breadth-first search, and post-order traversal, ensuring that the latency of noncritical paths matches that of critical paths, thereby enhancing data throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If buffers are assigned to balance throughput in dataflow paths, then data processing throughput is improved, but the number of buffers increases
Solution Approach 1:
The patent extracts and removes backedges from the dataflow graph, which are identified as causing throughput bottlenecks. By detecting backedges through graph traversal algorithms and systematically removing them, the method eliminates the need for excessive buffering while maintaining throughput balance, thus reducing the total number of buffers required
Solution Approach 2:
The patent performs preliminary buffer assignment to all paths before optimization, then iteratively removes buffers from non-critical paths after backedge removal. This preliminary action ensures that buffers are only retained where absolutely necessary for throughput balancing, minimizing the total buffer count while maintaining optimal data flow
2Stability of the object's composition
If backedges are present in the dataflow graph, then the graph structure is maintained, but data processing efficiency deteriorates
Solution Approach 1:
The patent detects backedges in the dataflow graph using graph traversal algorithms (depth-first search, breadth-first search, or post-order traversal) and systematically removes them. This extraction of backedges eliminates cyclic dependencies that cause processing inefficiencies while preserving the essential acyclic dataflow structure needed for efficient execution on CGRA devices
Solution Approach 2:
The patent dynamically adjusts the dataflow graph structure by iteratively detecting and removing backedges, then re-evaluating the graph to identify remaining cyclic dependencies. This dynamic transformation converts a potentially cyclic graph into an acyclic graph, optimizing data processing efficiency while maintaining the functional integrity of the computation
3Device complexity
If buffer insertion is performed without backedge removal, then implementation complexity is reduced, but latency balancing accuracy deteriorates
Solution Approach 1:
The patent segments the buffer insertion process into distinct phases: first removing backedges from the dataflow graph, then performing buffer insertion on the simplified acyclic graph. This segmentation handles the complexity of simultaneous backedge removal and buffer insertion by separating them into sequential steps, maintaining latency balancing accuracy while managing implementation complexity
Solution Approach 2:
The patent performs backedge removal as a preliminary action before buffer insertion. By eliminating backedges first, the method simplifies the subsequent buffer insertion process and enables more accurate latency balancing, as the buffer allocation algorithm operates on a cleaner acyclic graph structure without the confounding effects of cyclic dependencies
Data Source
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AI summary
Disclosed examples to insert buffers in dataflow graphs include: a backedge filter to remove a backedge between a first node and a second node of a dataflow graph, the first node representing a first operation of the dataflow graph, the second node representing a second operation of the dataflow graph; a latency calculator to determine a critical path latency of a critical path of the dataflow graph that includes the first node and the second node, the critical path having a longer latency to completion relative to a second path that terminates at the second node; a latency comparator to compare the critical path latency to a latency sum of a buffer latency and a second path latency, the second path latency corresponding to the second path; and a buffer allocator to insert one or more buffers in the second path based on the comparison performed by the latency comparator.