Buffer Insertion Using Edge Spacing and Stack Via Cost Function
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Solution Overview
Problem
Conventional buffer insertion techniques in integrated circuit design fail to account for edge spacing and stack via constraints, leading to sub-optimal buffering solutions and potential design rule violations.
Innovation Solution
A cost function is used during buffer insertion to account for edge spacing and stack via rules, determining candidate insertion locations and selecting buffering solutions based on these constraints to improve placement legalization and timing preservation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional buffer insertion techniques are used, then buffer insertion can be performed quickly, but edge spacing and stack via design rules are violated
Solution Approach 1:
The patent modifies the cost function parameters to include edge spacing and stack via constraints. By changing the evaluation criteria from purely timing-based to include geometric design rules, the buffer insertion process selects locations that satisfy both performance and manufacturing requirements simultaneously.
Solution Approach 2:
The patent introduces a placement legality check as an intermediary step between buffer insertion and placement legalization. This intermediate verification ensures that inserted buffers do not violate design rules, preventing the need for subsequent moves and maintaining both speed and compliance.
2Device complexity
If buffers are inserted without considering placement legality, then buffer insertion is simpler, but placement legalization becomes less efficient
Solution Approach 1:
The patent performs preliminary placement legality checks during the buffer insertion phase itself. By verifying design rule compliance before finalizing buffer locations, the system prevents future conflicts that would require time-consuming moves during placement legalization, thus improving overall efficiency without significantly increasing insertion complexity.
3Productivity
If buffer locations are not optimized for design rules, then buffer insertion is faster, but timing and design rule fixes are lost
Solution Approach 1:
The cost function is modified to include multiple parameters: timing metrics, edge spacing constraints, and stack via requirements. This multi-parameter optimization ensures that selected buffer locations simultaneously satisfy timing closure and design rule compliance, preserving both aspects without requiring separate correction passes.
Data Source
AI summary
Aspects of the present disclosure address improved systems and methods for buffer insertion in an integrated circuit (IC) design using a cost function that accounts for edge spacing and stack via constraints associated with cells in the IC design. An integrated circuit (IC) design comprising a routing topology for a net is accessed. A set of candidate insertion locations along the routing topology are identified. A set of buffering candidates is generated based on the candidate insertion locations. A buffering candidate comprises a cell inserted at a candidate insertion location along the routing topology. A cost associated with the buffering candidate is determined based on a number of potential edge spacing conflicts and a number of stack vias associated with the cell. A buffering solution for the net is selected from the buffering candidate based on the cost associated with the buffering candidate.