Integrated Circuit Buffer Interface for High-Speed Flow Control
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Solution Overview
Problem
In large dimension integrated electronic circuits operating at high clock frequencies, data buffers face challenges with fill status information propagation delays, leading to data loss due to the long electric conductors and high clock frequencies, and existing flow control methods are inefficient for managing data buffers within these circuits.
Innovation Solution
The solution involves a data transfer system with a receiving circuit having a data buffer and an output terminal for extraction information, and a sending circuit managing availability information updated on each data transmission or extraction, using multiple directional links for optimized flow control and improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FIFO buffers with fill status verification are used for data transmission, then data loss is prevented, but data transfer speed decreases due to waiting for status information
Solution Approach 1:
The invention pre-calculates and stores the number of words that can be sent to the buffer before transmission begins. This preliminary action eliminates the need to wait for fill status information during data transmission, as the sending circuit already knows the buffer capacity in advance, thus preventing data loss while maintaining high transfer speed
Solution Approach 2:
The invention introduces an intermediary counter that tracks the number of words the buffer can receive. This counter acts as a mediator between the sending and receiving circuits, allowing the sender to transmit data without direct real-time feedback about buffer fill status, thereby avoiding the speed penalty of traditional verification methods
2Reliability
If real-time fill status verification is implemented, then data loss is avoided, but propagation time delays increase
Solution Approach 1:
The system performs preliminary calculation of buffer capacity before data transmission starts. The number of words that can be sent is determined in advance and stored in a counter, eliminating the need for real-time status verification and the associated propagation time delays
3Reliability
If buffer capacity verification is performed before each transmission, then data integrity is maintained, but transmission frequency decreases
Solution Approach 1:
The invention calculates and stores the buffer capacity in advance in a counter. This preliminary action allows multiple data words to be transmitted consecutively without repeated verification, thereby maintaining data integrity while significantly increasing transmission frequency
Solution Approach 2:
Once the preliminary buffer capacity is established, the system enables continuous data transmission without interruption for status verification. The counter already contains the necessary information, allowing the transmission to proceed continuously at maximum speed
Data Source
AI summary
An interface having internal conductors to transfer data between a sending circuit and a receiving circuit in an integrated electronic circuit, the receiving circuit including an input buffer capable of receiving data and an output terminal for sending to the sending circuit an item of extraction information on each extraction of a data word from the input buffer, and the sending circuit including an enable circuit capable of activating an enable signal according to an item of availability information representative of the memory space available in the input buffer. The item of availability information is updated in the sending circuit on each transmission of a data word or on each receipt of the item of extraction information.