Semiconductor Buffer Layer Structure for Stable Breakdown Voltage
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Solution Overview
Problem
Conventional semiconductor devices with vertical structures, such as IGBTs and diodes, face issues with unstable breakdown voltage characteristics, high off-loss due to leakage current, poor controllability during turn-off operations, and reduced cutoff capability. These problems are exacerbated by crystal defects introduced during the formation of the N-type buffer layer.
Innovation Solution
The semiconductor device incorporates a novel N-type buffer layer structure with a two-layer design, comprising a first buffer layer with no detectable lattice defects and a second buffer layer with specific trap levels derived from lattice defects. This structure is formed using a photoluminescence method and is designed to improve the device's breakdown voltage characteristics and controllability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a conventional N-type buffer layer with high impurity concentration and steep gradient is used, then manufacturing is simplified, but breakdown voltage characteristics become unstable and off-loss increases
Solution Approach 1:
The N-type buffer layer is divided into multiple sub-layers with different impurity concentrations (first buffer layer with 1×10^16 to 1×10^17 atoms/cm³, second buffer layer with 1×10^15 to 1×10^16 atoms/cm³). This segmentation allows each sub-layer to contribute differently to device performance, achieving stable breakdown voltage characteristics while maintaining manufacturing feasibility through controlled impurity distribution.
Solution Approach 2:
Different regions of the buffer layer are assigned different impurity concentrations to achieve local optimization. The first buffer layer near the drift layer provides higher impurity concentration for better carrier control, while the second buffer layer farther from the drift layer has lower impurity concentration for reduced leakage current and improved breakdown voltage stability.
2Ease of manufacture
If high impurity concentration is provided in the buffer layer, then manufacturing is easier, but leakage current increases and off-loss increases
Solution Approach 1:
The buffer layer structure implements local quality optimization by positioning higher impurity concentration (first buffer layer) closer to the drift layer where carrier control is critical, and lower impurity concentration (second buffer layer) farther from the drift layer where leakage current reduction is prioritized. This spatial distribution of impurity concentrations achieves both ease of manufacture and reduced off-loss.
3Ease of manufacture
If steep impurity gradient is used in the buffer layer, then manufacturing is simplified, but controllability over turn-off operation deteriorates
Solution Approach 1:
The buffer layer is segmented into multiple sub-layers with gradually varying impurity concentrations rather than a single steep gradient. This segmentation provides intermediate steps in impurity concentration transition, enabling better control over carrier distribution and electric field formation during turn-off operation, while still maintaining manufacturing simplicity through a structured approach.
4Device complexity
If conventional buffer layer structure is used, then device complexity is reduced, but cutoff capability during turn-off is reduced
Solution Approach 1:
The buffer layer is divided into multiple sub-layers with different impurity concentrations, which appears to increase structural complexity but actually improves cutoff capability by providing better control over carrier extraction during turn-off. The segmented structure enables more effective electric field management and carrier removal, enhancing cutoff performance.
Solution Approach 2:
Different sub-layers of the buffer layer are assigned different impurity concentrations optimized for their specific locations and functions. The first buffer layer near the drift layer has higher impurity concentration for carrier control, while the second buffer layer has lower impurity concentration for efficient carrier extraction during turn-off, improving cutoff capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution achieves stable breakdown voltage characteristics, reduces off-loss by minimizing leakage current, enhances controllability during turn-off operations, and improves cutoff capability. Additionally, it mitigates the negative effects of crystal defects introduced during wafer processing.
Implementation Method 1
a first buffer layer in which a trap level derived from lattice defect is not detected by a photoluminescence method; and a second buffer layer provided between the first buffer layer and the drift layer and in which two types of trap levels derived from lattice defect are detected by the photoluminescence method
Data Source
AI summary
A semiconductor device includes: an N− drift layer of a first conductivity type formed in the semiconductor substrate; a P base layer formed on the N− drift layer; and an N buffer layer of the first conductivity type formed under the N− drift layer and higher in peak impurity concentration than the N− drift layer. The N buffer layer includes: a first buffer layer in which a trap level derived from lattice defect is not detected by a photoluminescence method; and a second buffer layer provided between the first buffer layer and the N− drift layer and in which two types of trap levels derived from lattice defect are detected by the photoluminescence method.