Buffer Layer CMP Stop for Dielectric Planarity

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Solution Overview

Problem

Chemical mechanical polishing (CMP) becomes unstable when addressing the interface between different oxide materials in coupled dielectric layers, leading to non-planar top surfaces and non-uniformity in pre-metallization dielectric (PMD) layers during integrated circuit fabrication.

Innovation Solution

A buffer layer is deposited on top of the first dielectric layer, extending through the trench, and used as a polish stop during CMP to protect the first dielectric material, ensuring planarity across the coupled dielectric structure formed by the first and second dielectric materials.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If CMP is performed directly on the coupled dielectric oxide layers without a buffer layer, then the process is simpler and faster, but the polish rate difference between different oxide materials causes non-planar top surfaces and thickness non-uniformity

Engineering Contradiction:

Improveplanarity of PMD layer top surfaceVSAvoidstructure of dielectric layers

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

A buffer layer made of a third oxide material is introduced between the first and second dielectric oxide layers. This intermediary layer has a polish rate that is intermediate between the two dielectric materials, allowing for stable and controlled polishing across the interface. The buffer layer acts as a mediator that prevents the polish rate mismatch from causing non-planarity, while being selectively removable afterward to reveal the final coupled dielectric structure with a planar top surface.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Manufacturing precision

If a buffer layer is added to achieve planarity during CMP, then the planarity and uniformity of the PMD layer improve, but the fabrication process becomes more complex with additional deposition and removal steps

Engineering Contradiction:

Improveuniformity of PMD layer thicknessVSAvoidfabrication process efficiency

Core Design Contradiction:

Manufacturing precisionVSProductivity

Solution Approach 1:

The buffer layer is deposited in advance before the second dielectric oxide layer, preparing the structure for subsequent CMP processing. This preliminary action ensures that when CMP is performed, the buffer layer is already in position to control the polish rate at the interface, preventing thickness non-uniformity from developing during the polishing process.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The buffer layer serves as a temporary structure that is discarded after fulfilling its purpose during CMP. After the CMP process completes and planarity is achieved, the buffer layer is selectively removed through etching, leaving behind the final coupled dielectric structure with the desired planar top surface and uniform thickness.

Inventive Principle:

Principle #34Discarding and recovering

3Adaptability or versatility

If different oxide materials are used for the first and second dielectric layers to achieve coupled dielectric structure, then the functional requirements are met, but the significant polish rate difference causes instability during CMP and non-planar surfaces

Engineering Contradiction:

Improvecoupled dielectric structure functionalityVSAvoidstability of CMP process

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The buffer layer made of a third oxide material serves as an intermediary between the two dielectric materials with different polish rates. This intermediary layer has a polish rate that falls between the rates of the first and second dielectric materials, creating a gradient that stabilizes the CMP process at the interface. The buffer layer absorbs the mismatch in polish rates, preventing the instability and non-planar surfaces that would otherwise occur when polishing directly across the interface of the coupled dielectric layers.

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The buffer layer effectively prevents erosion of the first dielectric material, achieving a substantially planar upper surface for the PMD layer with reduced thickness non-uniformity and dishing, enhancing the planarity and uniformity of the PMD layer.

Implementation Method 1

performing a chemical mechanical polish of the second dielectric layer, with the chemical mechanical polish using the buffer layer as a polish stop

Methodology Applied

Scientific EffectChemical mechanical polishing:

Data Source

PatentUS11211254B2Process for integrated circuit fabrication using a buffer layer as a stop for chemical mechanical polishing of a coupled dielectric oxide layer

Publication Date: 2021.12.28 STMICROELECTRONICS PTE LTD

AI summary

A first dielectric layer made of a first dielectric material is deposited over a semiconductor substrate. A buffer layer is then deposited on an upper surface of the first dielectric layer. A trench is opened to extend through the buffer layer and the first dielectric layer. A second dielectric layer made of a second dielectric material is the deposited in a conformal manner on the buffer layer and filling the trench. Chemical mechanical polishing of the second dielectric layer is performed to remove overlying portions of the second dielectric layer with the buffer layer being used as a polish stop. After removing the buffer layer, the first dielectric layer and the second dielectric material filling the trench form a pre-metallization dielectric layer having a substantially planar upper surface.