Buffer Layer Planarization for Thin Film Transistor Substrates
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Solution Overview
Problem
The existing methods for fabricating thin film transistor substrates often result in surface irregularities due to uneven buffer layers, leading to defects and reduced reliability of the thin film transistors, such as temporal afterimage and hysteresis.
Innovation Solution
The method involves forming a buffer layer with multiple insulating films, including silicon oxide and silicon nitride, and planarizing each layer using chemical mechanical polishing/planarization (CMP) to create a flat surface for the semiconductor layer, thereby preventing impurity diffusion and enhancing the substrate's planarity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single buffer layer is formed on the base substrate, then the manufacturing process is simple, but the surface planarity is insufficient leading to defects
Solution Approach 1:
The buffer layer is divided into multiple sub-layers (first buffer layer, second buffer layer, third buffer layer) with different materials and functions. Each sub-layer contributes to overall surface planarity while providing specific protective functions, resolving the contradiction between process simplicity and surface precision.
Solution Approach 2:
The buffer layer structure uses composite materials including silicon oxide, silicon nitride, and silicon oxynitride in different combinations. These composite material layers work together to achieve superior surface planarity and defect prevention compared to single-material buffer layers.
2Manufacturing precision
If multiple buffer layers are formed to improve surface planarity, then manufacturing precision improves, but device complexity increases
Solution Approach 1:
Different regions of the buffer layer structure have different material compositions and thicknesses optimized for specific local functions. The first, second, and third buffer layers have tailored properties to address specific planarity issues at different stages of fabrication, reducing overall device complexity while maintaining high precision.
3Productivity
If the buffer layer surface is not planarized, then the fabrication process is fast, but temporal afterimage and hysteresis defects occur
Solution Approach 1:
The buffer layer structure is designed with multiple pre-configured layers that inherently provide surface planarity before the active transistor fabrication begins. This preliminary planarization prevents defects like temporal afterimage and hysteresis from occurring during subsequent processing steps.
Solution Approach 2:
The multi-layer buffer structure acts as a cushioning layer that prevents defect formation in advance. By providing a planarized surface beforehand, it cushions against the formation of temporal afterimage and hysteresis defects during transistor operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the reliability of the thin film transistors by reducing surface irregularities and defects, resulting in better transistor characteristics, as evidenced by a decrease in threshold voltage change from 0.2038 to 0.1865, enhancing the overall performance and reliability of the thin film transistor substrate.
Implementation Method 1
Planarizing the surface of the buffer layer may be performed by chemical mechanical polishing/planarization (CMP).
Data Source
AI summary
A method for fabricating a thin film transistor substrate includes forming a buffer layer including at least one film on a base substrate, planarizing a surface of the buffer layer, and forming a thin film transistor on the buffer layer.