Integrated Circuit Package Bonding with Buffer Layer Plasma Shielding

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Solution Overview

Problem

The semiconductor industry faces challenges in bonding integrated circuit chips directly onto substrates due to the damage caused by high-density plasma processes to underlying conductive features, leading to plasma-induced damage and reduced yield and reliability of integrated circuit packages.

Innovation Solution

A buffer layer is formed over conductive features before depositing a high-density plasma oxide layer, acting as a barrier to prevent plasma damage, and a high power plasma process is used to deposit a robust bonding layer that increases density and durability, allowing seamless bonding with a carrier wafer while protecting the conductive features.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If high-density plasma process is used to deposit oxide layer, then bonding layer density and durability are improved, but conductive features suffer plasma-induced damage

Engineering Contradiction:
Improvebonding layer densityVSAvoidplasma damage to conductive features
Core Design Contradiction:
StrengthVSObject-affected harmful factors

Solution Approach 1:

A buffer layer is introduced as an intermediary between the conductive features and the high-density plasma oxide layer. This buffer layer absorbs the harmful plasma effects while allowing the high-density plasma process to proceed for depositing the bonding layer, thus protecting the conductive features from plasma-induced damage while maintaining bonding layer quality

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The buffer layer is formed in advance before depositing the high-density plasma oxide layer. This preliminary protective action prevents plasma damage to conductive features before the harmful plasma exposure occurs during the bonding layer deposition process

Inventive Principle:
Principle #10Preliminary action

2Productivity

If direct bonding of integrated circuit chip to substrate is attempted, then integration density is improved, but plasma process damage reduces yield and reliability

Engineering Contradiction:
Improveintegration densityVSAvoidpackage yield
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The buffer layer serves as a protective intermediary that enables direct chip-to-substrate bonding while preventing plasma-induced damage to conductive features. This allows high integration density to be achieved without compromising package yield and reliability

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

By forming the buffer layer before the high-density plasma oxidation process, the patent preliminarily protects the conductive features, enabling subsequent direct bonding operations to proceed without damage and thus maintaining both high integration density and reliable package yield

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method improves the yield and reliability of integrated circuit packages by preventing plasma-induced damage to conductive features and forming a robust bond with the carrier wafer, enhancing the structural integrity and functionality of the integrated circuits.

Implementation Method 1

a plasma process is performed to deposit the bonding layer

Methodology Applied
Scientific EffectPlasma: Plasma

Implementation Method 2

a high power plasma process is used to deposit a robust bonding layer that increases density and durability

Methodology Applied
Scientific EffectPlasma Enhanced Chemical Vapour Deposition: Plasma Enhanced Chemical Vapour Deposition

Data Source

PatentUS11908829B2Integrated circuit package and method of forming same
Publication Date: 2024.02.20 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11908829B2 patent drawing
  • US11908829B2 patent drawing
  • US11908829B2 patent drawing

AI summary

In an embodiment, a method includes performing a first plasma deposition to form a buffer layer over a first side of a first integrated circuit device, the first integrated circuit device comprising a first substrate and a first interconnect structure; performing a second plasma deposition to form a first bonding layer over the buffer layer, wherein a plasma power applied during the second plasma deposition is greater than a plasma power applied during the first plasma deposition; planarizing the first bonding layer; forming a second bonding layer over a second substrate; pressing the second bonding layer onto the first bonding layer; and removing the first substrate.