Buffer Layer Positioning Region for TFT Alignment
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Solution Overview
Problem
Oxide semiconductor thin film transistors (TFTs) face alignment difficulties due to high light transmittance, and increasing channel thickness to reduce transmittance leads to threshold voltage shifts, making it challenging to achieve high alignment accuracy without altering the semiconductor thickness.
Innovation Solution
Incorporating a buffer layer with a positioning region of greater thickness than the surrounding areas, which serves as a positioning mark, allowing for precise alignment during the fabrication process, and using a secondary insulation layer to maintain a flat surface and avoid plasma damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the thickness of the oxide semiconductor channel is increased to decrease light transmittance, then alignment accuracy is improved, but threshold voltage shifts occur
Solution Approach 1:
The invention divides the buffer layer into two distinct thickness regions: a first thickness region (thicker) and a second thickness region (thinner). This segmentation allows the channel to serve as an alignment mark for high measurement precision while maintaining the original thin channel thickness to avoid threshold voltage shifts. The alignment mark function is transferred from the channel to the buffer layer's thickness variation.
Solution Approach 2:
The buffer layer is designed with non-uniform thickness, having a first thickness in a first region and a second thickness in a second region. This local quality variation creates distinct alignment marks without affecting the overall channel thickness, enabling precise alignment while maintaining electrical performance.
2Illumination intensity
If the thickness of the oxide semiconductor channel is kept thin to maintain high light transmittance, then light transmittance is improved, but alignment accuracy deteriorates
Solution Approach 1:
The buffer layer acts as an intermediary element that provides alignment marks through its thickness variation. This allows the thin channel to maintain high light transmittance while the buffer layer's thickness difference serves as the alignment reference, decoupling the alignment function from the channel thickness.
Solution Approach 2:
Instead of using channel thickness (vertical dimension) for alignment, the invention uses the buffer layer's thickness variation in the vertical dimension to create alignment marks, allowing the channel to remain thin for optical performance.
Data Source
AI summary
An active device and a fabricating method thereof are provided. The active device includes a buffer layer, a channel, a gate, a gate insulation layer, a source and a drain. The buffer layer is disposed on a substrate and has a positioning region. A thickness of a portion of the buffer layer in the positioning region is greater than a thickness of a portion of the buffer layer outside the positioning region. The channel is disposed on the buffer layer and in the positioning region. The gate is disposed above the channel. The gate insulation layer is disposed between the channel and the gate. The source and the drain are disposed above the channel and electrically connected to the channel.