Buffer Layer Mitigates Thermal Stress in Semiconductor Conductive Vias
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing semiconductor devices with through silicon vias (TSV) technique face reliability issues due to stress concentration at the interface between conductive bumps and TSVs during the reflowing process, leading to potential cracking and reduced product yield.
Innovation Solution
A semiconductor device design that includes a substrate with conductive vias, an insulating layer exposing the end portions of the vias, a buffer layer on the insulating layer or dielectric layer periphery, and a redistribution layer to mitigate stress concentration by forming a buffer layer on the periphery of the conductive vias and dielectric layer openings, thereby reducing thermal stress during the reflowing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive bumps are soldered on UBM via reflowing method, then electrical connection is achieved, but stress concentration occurs at the interface between conductive bumps and through silicon vias
Solution Approach 1:
The patent introduces a buffer layer as an intermediary component between the conductive bump and the through silicon via. This buffer layer absorbs and distributes the thermal stress generated during the reflowing process, preventing stress concentration at the interface. The buffer layer acts as a mediator that decouples the thermal expansion differences between the conductive bump and the rigid via structure, thereby improving device reliability without compromising the electrical connection function.
Solution Approach 2:
The patent modifies the structural parameters at the interface by adding a buffer layer with specific material properties and geometric dimensions. This changes the stress distribution parameters in the reflowing process, transforming the concentrated stress into distributed stress across the buffer layer. The parameter change approach allows the system to maintain electrical connectivity while reducing peak stress values that cause cracking.
2Stress or pressure
If buffer layer is formed on peripheries of conductive vias, then stress concentration is reduced, but device structure becomes more complex
Solution Approach 1:
The buffer layer is not applied uniformly across the entire device but is strategically positioned only at the peripheries of the conductive vias where stress concentration occurs during reflowing. This localized application approach addresses the specific problem area without unnecessarily complicating the overall device structure. The local quality principle allows the buffer layer to perform its stress-reduction function while maintaining simplicity in non-critical areas of the device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The buffer layer significantly reduces thermal stress, improving the reliability of the semiconductor device and increasing product yield by approximately 24% compared to prior art, as verified experimentally.
Implementation Method 1
the remaining stresses due to the heat will concentrate on the interface between the conductive bumps 14 and the through silicon vias 11
Data Source
AI summary
A semiconductor device is provided, including: a substrate having opposing first and second surfaces and a plurality of conductive vias passing through the first and second surfaces; an insulating layer formed on the first surface of the substrate and exposing end portions of the conductive vias therefrom; and a buffer layer formed on the insulating layer at peripheries of the end portions of the conductive vias, thereby increasing product reliability and good yield.