Level Shifter and Buffer Timing for Stable Power-On Data Retention
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Solution Overview
Problem
Semiconductor devices with oxide transistors face data loss due to unintentional high-level potential output when power supply voltages are reapplied, leading to instability in the off-state of transistors and potential data retention issues.
Innovation Solution
A semiconductor device structure incorporating a first buffer circuit, a level shifter circuit, and a second buffer circuit, where the power supply voltage is applied by switching potentials between different timings to the first and second wirings, ensuring a low-level potential is maintained at the gate of the transistor, preventing data loss and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If power supply voltages are supplied to the booster circuit to raise signal voltage for controlling the OS transistor, then the signal amplitude is sufficient for transistor control, but unintentional high-level potential may be supplied to the gate causing data loss
Solution Approach 1:
The invention applies preliminary action by setting the potential of the first wiring (connected to the gate of the OS transistor) to a low-level potential (third potential) before reapplying power supply voltages. This preliminary potential setting prevents the gate from receiving unintentional high-level potential during power resumption, thereby avoiding data loss while allowing the booster circuit to generate sufficient signal amplitude for transistor control.
2Power
If multiple power supply voltages are used for the booster circuit to achieve large signal amplitude, then the transistor control is effective, but the device complexity and power consumption increase
Solution Approach 1:
The invention applies segmentation by dividing the power supply configuration into distinct potential levels: a first potential (VDD1) for normal operation, a second potential (VDD2, higher than VDD1) for boosting signal amplitude in the booster circuit, and a third potential (lower than VDD1) for the first wiring to prevent unintentional high-level potential. This segmented approach allows the booster circuit to use multiple voltage levels for effective transistor control while the separate control of the first wiring simplifies the overall device complexity by preventing data loss through dedicated low-level potential application.
3Reliability
If the first wiring potential is switched from third potential to first potential before second wiring potential switching, then data loss is prevented, but the control timing complexity increases
Solution Approach 1:
The invention applies preliminary action by establishing a predetermined control timing sequence where the potential of the first wiring is switched from the third potential to the first potential before the potential of the second wiring is switched from the third potential to the second potential. This preliminary sequencing ensures that the gate of the OS transistor is safely at a low-level potential before the booster circuit receives higher voltage, preventing data loss. The predetermined nature of this timing sequence simplifies control implementation while maintaining reliability.
Data Source
AI summary
To provide a semiconductor device that inhibits unexpected output of a high-level signal immediately after the rise of a power supply voltage. A semiconductor device includes a first buffer circuit, a level shifter circuit, and a second buffer circuit. A first potential is supplied to the first buffer circuit, and a second potential is supplied to the level shifter circuit and the second buffer circuit; consequently, the semiconductor device returns to a normal state. The first potential is supplied to the first buffer circuit before the second potential is supplied to the level shifter circuit and the second buffer circuit, whereby the operations of the level shifter circuit and the second buffer circuit can be controlled. This inhibits unexpected output of a high-level signal to a wiring connected to the second buffer circuit.