Buffer Management Architecture Using Allocation and Reclaim SRAM

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Solution Overview

Problem

Network switches face challenges in managing buffer memory efficiently, particularly when packets get stuck due to errors or port malfunctions, leading to buffer allocation and clearance issues.

Innovation Solution

A buffer management module with Allocation SRAM and Reclaim SRAM is implemented, which allocates and clears buffers dynamically, using a state machine to manage buffer allocation and a reclaim mechanism to identify and free stuck buffers, ensuring continuous network operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If buffers are allocated dynamically in buffer memory, then network switch flexibility and packet routing capability are improved, but buffer management complexity and risk of buffer allocation errors increase

Engineering Contradiction:
Improvebuffer allocation flexibilityVSAvoidbuffer management complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The buffer memory is divided into multiple lines, with each line containing multiple buffers. The allocation register stores only the current line being allocated, while the SRAM stores all lines with their allocation states. This segmentation allows complex buffer management to be broken down into simpler line-based operations, reducing management complexity while maintaining flexibility.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an allocation register as an intermediary between the buffer management module and the SRAM. This register acts as a buffer/cache that holds the current line data, reducing direct access complexity to the full SRAM structure. The intermediary simplifies the management interface while maintaining the ability to manage all buffers in the system.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If buffer allocation is tracked using SRAM, then buffer allocation accuracy and reliability are improved, but memory resource consumption increases

Engineering Contradiction:
Improvebuffer allocation accuracyVSAvoidmemory resource consumption
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The allocation tracking is segmented into two parts: the allocation register which holds the current line being managed (reducing immediate memory access needs) and the SRAM which stores the complete allocation state of all buffers. This segmentation allows accurate tracking of all buffers while optimizing memory access patterns and reducing the memory footprint of actively managed data.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent organizes buffer allocation tracking in a two-dimensional structure where buffers are arranged in lines, and the allocation register works with one line at a time while the SRAM stores multiple lines. This dimensional organization allows efficient memory usage by processing buffers in manageable line-sized chunks rather than requiring all buffer states to be simultaneously accessible.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Productivity

If the allocation register stores all buffer lines, then buffer allocation speed is improved, but register size and hardware resource requirements increase

Engineering Contradiction:
Improvebuffer allocation speedVSAvoidallocation register size
Core Design Contradiction:
ProductivityVSVolume of stationary object

Solution Approach 1:

The buffer allocation functionality is segmented between the allocation register and the SRAM. The allocation register only needs to store the current line being allocated (one line at a time), while the SRAM stores all buffer lines. This segmentation enables fast allocation operations using the small register while maintaining comprehensive buffer management capability through the larger SRAM, avoiding the need for an excessively large register.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs preliminary action by pre-organizing buffer allocation data in the SRAM in line-based structures before allocation operations occur. This allows the allocation register to work with pre-prepared line data, enabling fast allocation without requiring the register to hold all possible buffer states simultaneously. The SRAM is prepared in advance to supply line data to the register as needed.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS7689793B1Buffer management architecture
Publication Date: 2010.03.30 MARVELL ISRAEL (M L S L) LTD
  • US7689793B1 patent drawing
  • US7689793B1 patent drawing
  • US7689793B1 patent drawing

AI summary

A network switch may include a buffer management module to manage buffers in a buffer memory. The buffer management module may include an Allocation SRAM and a Reclaim SRAM. Each buffer in the buffer memory may be associated with a corresponding bit in the Allocation SRAM and Reclaim SRAM. A line including bits indicating available buffers in the Allocation SRAM may be written to the allocation register, and the buffer management module may allocate buffers from the allocation register. A reclaim module may age bits in the Reclaim SRAM. The reclaim module may reclaim buffers by searching corresponding lines in the Allocation SRAM and Reclaim SRAM and comparing the values of bits in the two lines.