Buffer Manager for Concurrent Memory Allocation in Network Devices

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Network devices with multiple switching cores face inefficiencies in memory management, as each core can only access its own memory, limiting shared memory utilization and bandwidth across cores.

Innovation Solution

Implementing a buffer manager that allows multiple processing cores to share a memory space, enabling simultaneous allocation and clearing of buffers across cores within a single clock cycle, with a linking table to manage multi-buffer packets and optimize memory usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If each switching core is coupled to a respective memory, then memory access is simple and direct, but memory space cannot be shared among multiple cores

Engineering Contradiction:
Improvememory sharing capabilityVSAvoidmemory management complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

A buffer manager is introduced as an intermediary component between multiple switching cores and a shared memory space. The buffer manager receives allocation requests from multiple cores, manages the shared memory space, and grants access to appropriate buffers. This mediator enables memory sharing while centralizing management logic, thus achieving adaptability without proportionally increasing overall system complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If multiple cores share a memory space, then memory utilization improves, but allocation coordination becomes complex

Engineering Contradiction:
Improvememory utilization efficiencyVSAvoidallocation request coordination
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The buffer manager implements self-service mechanisms by automatically managing buffer allocation and tracking the state of the shared memory space. When allocation requests are received, the buffer manager autonomously determines buffer availability, grants access rights, and updates internal state without requiring complex inter-core coordination protocols. This self-managing approach improves memory utilization while keeping coordination complexity contained within the buffer manager itself.

Inventive Principle:
Principle #25Self-service

3Productivity

If buffers are allocated in separate clock cycles, then allocation is simple, but bandwidth and efficiency are reduced

Engineering Contradiction:
Improvememory operation throughputVSAvoidconcurrent operation management
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The buffer manager performs preliminary actions by pre-establishing the allocation logic and buffer state tracking mechanisms before multiple cores begin their operations. By having the buffer manager ready with pre-configured allocation rules and state information, multiple allocation requests can be processed in parallel within a single clock cycle without requiring complex runtime coordination, thus improving throughput while managing complexity through advance preparation.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9996468B1Scalable dynamic memory management in a network device
Publication Date: 2018.06.12 MARVELL ISRAEL (M L S L) LTD
  • US9996468B1 patent drawing
  • US9996468B1 patent drawing
  • US9996468B1 patent drawing

AI summary

In a method for managing memory space in a network device two or more respective allocation requests from two or more processing cores among a plurality of processing cores sharing a memory space are received at a memory management device during a first single clock cycle of the memory management device, the two or more allocation requests requesting to allocate, to the two or more processing cores, respective buffers in the shared memory space. In response to receiving the two or more allocation requests, the memory management device allocates to the two or more processing cores, respective two or more buffers in the shared memory space. Additionally, the management device, during a second single clock cycle of the memory management device, transmits respective allocation responses to each of the two or more processing cores, wherein each allocation response includes an indication of a respective allocated buffer.