Buffer Memory Cache Allocation for Storage Device Speed
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Solution Overview
Problem
Current storage devices face inefficiencies in data access and processing speed due to the need to constantly access main memory, which limits the operation speed of host and storage devices.
Innovation Solution
Implementing a storage device with a buffer memory that allocates a portion of its mapping area to a cache area, allowing data to be cached in advance and reducing the reliance on main memory access, thereby improving operation speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is stored and accessed through main memory, then data access is possible, but operation speed is limited due to constant main memory access requirements
Solution Approach 1:
The buffer memory is segmented into a mapping area and a cache area. The mapping area stores mapping data indicating mapping relationships between logical block addresses and physical block addresses, while the cache area stores actual data. This segmentation allows the system to simultaneously maintain address translation functionality and data caching capability, enabling direct access to cached data without requiring main memory access for every operation.
Solution Approach 2:
The buffer memory acts as an intermediary between the host device and the storage device. By allocating a cache area within the buffer memory, frequently accessed data can be stored locally in the storage device's buffer, serving as a mediator that eliminates the need for repeated main memory access while maintaining data availability for the host.
2Productivity
If main memory is used for data caching, then data access speed improves, but host device resources are consumed
Solution Approach 1:
The storage device provides self-service by allocating its own buffer memory resources to create a cache area. Instead of relying on the host device's main memory for caching operations, the storage device utilizes its internal buffer memory (segmented into mapping and cache areas) to cache data independently, thereby improving data processing speed without consuming host device memory resources.
3Measurement precision
If the entire buffer memory is used for mapping data, then address translation is accurate, but cache functionality is reduced
Solution Approach 1:
The buffer memory allocation is made dynamic through the allocation request mechanism. The host device can issue allocation requests to dynamically adjust the size of the cache area within the buffer memory. This allows the system to adapt cache allocation flexibility based on workload requirements while maintaining sufficient mapping area for accurate address translation, resolving the contradiction between mapping precision and cache versatility.
Data Source
AI summary
The present technology relates to a storage device that allows access to the storage device without accessing a main memory of a host by allocating a portion of a mapping area of a buffer memory to a cache area. The storage device includes a memory device including a plurality of memory cells, a memory controller configured to control an operation performed on the memory device, and a buffer memory including a cache area and a mapping area in which mapping data indicating a mapping relationship between a logical block address and a physical block address corresponding to the operation is stored. The buffer memory allocates a portion of the mapping area to the cache area according to an allocation request received from a host, and stores data except for the mapping data in the cache area.