Buffer Memory Flag Cell Array for Background Error Correction
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Solution Overview
Problem
Current semiconductor memory systems face limitations in real-time data error correction as the bandwidth of the data bus increases, restricting the amount of data that can be corrected simultaneously.
Innovation Solution
A semiconductor memory system that utilizes a buffer memory with a flag cell array and error correction block to perform error correction on data stored in the buffer memory, allowing for efficient error correction even when the host is not actively using the system, by using a flag sense amplifier, controller, and error correction logic to generate signals and output corrected data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If real-time error correction is performed on data with increased bandwidth, then data integrity is maintained, but the system cannot correct all data simultaneously due to bandwidth limitations
Solution Approach 1:
The patent performs error correction in advance during background operations before data is actually needed. The controller proactively corrects errors in the buffer memory during idle periods or when data is not being actively accessed, so that when data is subsequently read, it is already corrected and ready for immediate use. This eliminates the need for time-critical error correction during high-bandwidth data operations.
Solution Approach 2:
The patent introduces a flag cell array as an intermediary mechanism to track the error correction status of data in the buffer memory. These flag cells store status information (whether error correction has been performed) without interfering with the main data flow. The flag sense amplifier reads these status flags to determine which data requires correction, enabling efficient management of error correction tasks without bottlenecking the data bus.
2Reliability
If error correction is performed during active host operations, then data accuracy is ensured, but system performance deteriorates due to resource contention
Solution Approach 1:
The patent implements periodic background error correction operations that execute during idle periods or low-activity intervals. The controller periodically checks the flag cell array and performs error correction on flagged data during these intervals, rather than continuously interrupting active operations. This periodic approach ensures data accuracy is maintained while minimizing impact on system performance during high-speed data transfers.
Solution Approach 2:
The system performs error correction as a self-service background task that automatically manages itself without requiring host intervention. The controller autonomously monitors the buffer memory, identifies data requiring correction through the flag cells, and executes correction operations independently during background periods. This self-service mechanism ensures data accuracy while freeing up system resources for primary data transfer operations.
3Ease of operation
If a flag cell array is added to track error correction status, then error correction management is improved, but device complexity increases
Solution Approach 1:
The patent segments the buffer memory into distinct functional components: data storage cells and flag cells. Each data element in the buffer has an associated flag cell that independently tracks its error correction status. This segmentation allows the system to manage error correction information separately from the main data, simplifying the control logic and making error tracking more efficient without significantly complicating the overall memory structure.
Solution Approach 2:
The flag cell array serves multiple functions: it tracks error correction status, enables the controller to identify which data needs correction, and provides status information to the flag sense amplifier. This multi-functionality reduces the need for separate mechanisms for each task, thereby managing complexity efficiently while providing comprehensive error correction management capabilities.
Data Source
AI summary
A buffer memory includes a memory cell array, a flag cell array, and a error correction block. The memory cell array has a plurality of word lines. Each of the plurality of word lines are electrically connected to a plurality of memory cells storing data. The flag cell array has a plurality of flag cells. Each of the plurality of flag cells is connected to each of the word lines and stores information that indicates whether error correction of the data has been performed. The error correction block performs error correction on the data output from the memory cell array in response to a command received through a host interface and flag data output from the flag cell array.