Buffer Memory Management for Read Speed Optimization

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Solution Overview

Problem

The existing memory storage devices with rewritable non-volatile memory face a significant drop in read speed due to the large size of the logical unit-buffer unit mapping table when the buffer memory is filled with data, leading to increased read times and decreased overall function.

Innovation Solution

A data access method that counts the accumulative data of consecutive read commands and writes data from the buffer memory into a rewritable non-volatile memory module when the data threshold is reached, thereby omitting the need to search the logical unit-buffer unit mapping table and preventing the slowdown caused by an enlarged mapping table.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the buffer memory stores a large amount of data, then the buffer memory can serve more read requests, but the time to search the logical unit-buffer unit mapping table increases significantly

Engineering Contradiction:
Improveamount of data in buffer memoryVSAvoidread time
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The patent segments the mapping table search process by introducing a buffer management mechanism that divides data into buffer units with associated mapping entries. When the buffer contains many data units, the system segments the search space by checking buffer hits first (O(1) access) before falling back to full mapping table search, effectively breaking down the large-scale search problem into smaller, manageable segments.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary actions by pre-establishing the logical unit-buffer unit mapping table before read operations occur. This mapping table is built in advance during data loading, so when read requests arrive, the system can quickly check the pre-computed mapping relationships without performing complex searches during the actual read operation, reducing latency.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If the buffer memory is filled with data, then more data can be served quickly, but the mapping table size increases causing slower read operations

Engineering Contradiction:
Improvedata serving capacityVSAvoidmapping table size
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements dynamic buffer management where the buffer memory capacity and mapping table size adjust based on workload conditions. The system dynamically allocates buffer units, updates mapping entries selectively, and can evict less frequently accessed data, allowing the mapping table size to remain manageable even as overall buffer capacity increases to serve more requests.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes key parameters including buffer unit size, mapping table organization structure, and data eviction thresholds based on system conditions. By adjusting these parameters, the system optimizes the balance between buffer capacity (for serving more requests) and mapping table complexity (for maintaining fast access), adapting to different workload scenarios.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10191659B2Buffer memory management method, memory control circuit unit and memory storage device
Publication Date: 2019.01.29 PHISON ELECTRONICS
  • US10191659B2 patent drawing
  • US10191659B2 patent drawing
  • US10191659B2 patent drawing

AI summary

A data access method for a memory storage device is provided. The memory storage device includes a rewritable non-volatile memory module and a buffer memory. The method includes: receiving at least one operation command including at least one read command; and counting an amount of accumulative data of the at least one read command, and if the amount of accumulative data reaches a data threshold, writing the data in the buffer memory into the rewritable non-volatile memory module.