Buffer Memory Management for Asynchronous Multi-Plane Operations
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Solution Overview
Problem
In memory storage devices with rewritable non-volatile memory modules, the limited capacity of buffer memory often leads to insufficient available space, necessitating a mechanism to quickly and temporarily release storage space for operations requiring more temporary space.
Innovation Solution
A memory management method and circuit unit that temporarily transfers data from the buffer memory to a register of a memory plane, releasing buffer memory space for operations on another plane, allowing asynchronous operations and increasing available buffer memory space by using the released space for operations like bad block replacement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the buffer memory capacity is increased to provide sufficient available space, then the storage space availability is improved, but the device cost increases
Solution Approach 1:
The patent implements a dynamic buffer management mechanism that temporarily transfers data from buffer memory to memory plane registers when buffer space is insufficient. This dynamic allocation allows the buffer to adapt its available capacity based on operational needs, effectively increasing usable buffer space without physically expanding the buffer memory hardware, thereby avoiding increased device cost while maintaining sufficient available space for operations.
Solution Approach 2:
The system changes the operational parameters of the buffer memory by utilizing the register resources of memory planes as extended buffer space. By changing the state of data storage from exclusively buffer memory to a combined buffer-memory plane register system, the effective buffer capacity is increased without adding physical buffer memory components, thus resolving the cost constraint.
2Quantity of substance
If data is transferred from buffer memory to memory plane register to release buffer space, then the available buffer space is improved, but the data transfer time and operation complexity increase
Solution Approach 1:
The patent performs preliminary actions by transferring data to memory plane registers before the buffer space is actually needed. The system monitors buffer usage and proactively moves data to plane registers in advance, so that when buffer space is required for critical operations, it is already available without causing delays. This preliminary action reduces the actual data transfer time when space is urgently needed.
Solution Approach 2:
The memory plane register serves as an intermediary storage location between the buffer memory and the final data destination. By using the plane register as a temporary holding location, the system can release buffer space efficiently while maintaining data accessibility. The intermediary role of the plane register minimizes the time penalty by providing a nearby storage location that requires minimal transfer time compared to alternative approaches.
3Reliability
If the buffer memory space is used for operations on one memory plane, then the operation completeness is improved, but the capacity for handling operations on other planes is reduced
Solution Approach 1:
The patent segments the buffer memory usage by plane, allowing different portions of buffer space to be allocated to different memory planes based on their specific operation needs. By segmenting the buffer management per plane and utilizing plane-specific registers, the system can ensure complete operations for one plane while simultaneously maintaining capacity to handle operations on other planes, thus improving both operation completeness and multi-plane adaptability.
Solution Approach 2:
The memory plane registers serve multiple functions: they act as data storage for their respective planes, serve as extended buffer space when needed, and enable asynchronous operations across multiple planes. This multi-functionality allows the system to maintain operation completeness for any given plane while simultaneously supporting versatile multi-plane operations, as the same register resources can be dynamically allocated to different planes based on operational requirements.
Data Source
AI summary
The present invention relates to a memory management method, memory control circuit unit, and a memory storage device. The method includes: transmitting temporary data from a buffer memory to a register of a first memory plane; releasing a first storage space of the buffer memory, wherein the first storage space is configured to store the temporary data; performing a first operation to a second memory plane by using the first storage space; and after finishing the first operation performed on the second memory plane, reloading the temporary data from the register of the first memory plane to the first storage space of the buffer memory, wherein operations performed on the first memory plane and the second memory plane are asynchronous operations.