Buffer Lower Metal Line for Semiconductor Impact Absorption
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Solution Overview
Problem
High voltage semiconductor devices suffer physical damage during wire bonding due to direct transmission of impact, and existing metal lines have high resistance, affecting the reliability of the package and circuit integrity.
Innovation Solution
A method involving the formation of a buffer lower metal line with a thickness of 1 μm to 2 μm over the semiconductor substrate to absorb external impacts, combined with a pre-metal-dielectric layer, seed layer, and a thick upper metal line with a copper layer and interface metal layers like Ni, Pd, and Au, to reduce physical stress and resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a thin lower metal line (4000 Å AlCu) is used, then the device structure is simple and manufacturing is easier, but physical damage occurs during wire bonding due to direct impact transmission
Solution Approach 1:
The lower metal line is segmented into two distinct parts: a buffer lower metal line (1 μm to 2 μm thick) for impact absorption and a standard thickness lower metal line for electrical connectivity. This segmentation allows each part to perform its specific function optimally without compromising the other.
Solution Approach 2:
A buffer lower metal line with increased thickness (1 μm to 2 μm) is formed beforehand to absorb external impacts during wire bonding. This cushioning layer is positioned between the bonding pad and the standard thickness lower metal line, preventing direct transmission of impact forces to the underlying device structure.
2Reliability
If a thick buffer lower metal line (1 μm to 2 μm) is added for impact absorption, then reliability during bonding improves, but manufacturing complexity and process steps increase
Solution Approach 1:
The buffer lower metal line is formed during the preliminary stages of metal line fabrication, before via hole formation and upper metal line deposition. By incorporating the buffer layer into the existing fabrication sequence, the patent minimizes additional process steps while ensuring impact protection is built into the structure from the outset.
3Strength
If the lower metal line thickness is increased to absorb impact, then physical damage is prevented, but metal line resistance increases
Solution Approach 1:
The lower metal line is divided into a buffer section with increased thickness (1 μm to 2 μm) for impact absorption and a standard thickness section for optimal electrical conductivity. This segmentation ensures that the thicker portion serves mechanical protection while the standard thickness portions maintain low resistance electrical pathways.
Solution Approach 2:
The buffer lower metal line with increased thickness is localized specifically at regions requiring impact absorption (near bonding pads), while other regions maintain standard metal line thickness. This local quality adjustment ensures impact protection is provided only where needed, without unnecessarily increasing resistance in the entire metal line network.
4Reliability
If a multi-layered metal line structure is employed, then high voltage device reliability improves, but the risk of physical damage during wire bonding increases due to direct impact transmission
Solution Approach 1:
The buffer lower metal line serves as a cushioning layer that absorbs external impacts during wire bonding before the forces can reach the underlying device structure. This beforehand cushioning protects the multi-layered metal line structure and underlying devices from physical damage while maintaining the operational reliability benefits of the multi-layered configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dual thick metal line structure effectively absorbs and attenuates physical impacts during bonding, enhancing the reliability of the semiconductor device package and reducing resistance, thereby protecting the circuit and improving the device's operational stability.
Implementation Method 1
forming a buffer lower metal line over a semiconductor substrate for absorbing an external impact
Implementation Method 2
an upper metal line which includes a copper layer formed over the copper seed layer
Implementation Method 3
subjecting the semiconductor substrate having the upper metal line formed thereon to a thermal process
Implementation Method 4
removing the polyimide by dry etching
Data Source
AI summary
A method includes forming a buffer lower metal line over a semiconductor substrate for absorbing an external impact, forming a pre-metal-dielectric layer which covers the buffer lower metal line, the pre-metal-dielectric layer having a via hole formed therein to expose a portion of the buffer lower metal line, forming a seed layer over a surface of the pre-metal-dielectric layer having the via hole formed therein, forming polyimide which exposes the via hole and the seed layer formed over the pre-metal-dielectric layer in the vicinity of the via hole, growing an upper metal line over the exposed seed layer, subjecting the semiconductor substrate having the upper metal line formed thereon to a thermal process, removing the polyimide by dry etching, and bonding a bonding portion onto the upper metal line.