Buffer Mini-Cache for DRAM Access Power Conservation
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Solution Overview
Problem
Microprocessor systems face inefficiencies in power consumption and performance due to significant DRAM accesses during DMA operations, especially when processors are in low-power states, and the need for coherent DMA processing across various ACPI-compliant states.
Innovation Solution
Implementing a small, power-efficient buffer/mini-cache that can satisfy non-cacheable and background DMA device accesses, allowing the CPU and cache subsystem to remain in low-power states by processing these accesses instead of DRAM, with operational modes transitioning between cacheable and non-cacheable access modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If DRAM accesses are performed during DMA operations when processor is in low-power state, then DMA operations can be completed, but power consumption increases significantly
Solution Approach 1:
The cache is pre-filled with data from DRAM before the processor enters low-power state. This preliminary action ensures that when DMA operations need to access memory during low-power state, the data is already available in the cache, eliminating the need for high-power DRAM accesses during the low-power period.
Solution Approach 2:
The cache acts as an intermediary between the DMA operations and DRAM. During low-power states, DMA operations access the cache instead of directly accessing DRAM, which would require high power. The cache mediates these accesses, allowing DMA functionality while maintaining low power consumption.
2Reliability
If processor and cache subsystem are powered up to process coherent DMA operations, then coherent DMA can be performed, but power consumption increases
Solution Approach 1:
The coherent DMA processing capability is extracted from the main processor and implemented in the I/O bus controller. This allows coherent DMA operations to be performed independently without requiring the full processor to be powered up, thereby maintaining reliability while reducing power consumption.
Solution Approach 2:
The system is segmented such that different components have different power states. The I/O bus controller can remain in a lower power state while still handling coherent DMA operations, while the main processor can be fully powered down. This segmentation allows selective operation of subsystems based on actual needs.
3Use of energy by moving object
If cache is used to satisfy DMA accesses during low-power state, then power consumption is reduced, but cache coherence management complexity increases
Solution Approach 1:
The cache is designed to automatically handle DMA accesses during low-power states without requiring complex external coherence management. The cache inclusion policy and automatic invalidation mechanisms provide self-service coherence management, reducing the burden on external controllers while maintaining power efficiency.
Data Source
AI summary
Power conservation via DRAM access reduction is provided by a buffer/mini-cache selectively operable in a normal mode and a buffer mode. In the buffer mode, entered when CPUs begin operating in low-power states, non-cacheable accesses (such as generated by a DMA device) matching specified physical address ranges, or having specific characteristics of the accesses themselves, are processed by the buffer/mini-cache, instead of by a memory controller and DRAM. The buffer/mini-cache processing includes allocating lines when references miss, and returning cached data from the buffer/mini-cache when references hit. Lines are replaced in the buffer/mini-cache according to one of a plurality of replacement policies, including ceasing replacement when there are no available free lines. In the normal mode, entered when CPUs begin operating in high-power states, the buffer/mini-cache operates akin to a conventional cache and non-cacheable accesses are not processed therein.