Buffer Module Integration in Coating Developing Systems
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Solution Overview
Problem
The existing coating and developing systems for semiconductor wafers or LCD substrates face inefficiencies due to differences in processing rates between the exposure system and the coating and developing system, leading to increased manufacturing costs and footprint, as well as potential yield reduction when the exposure system is stopped or operates at a lower rate.
Innovation Solution
A coating and developing system with vertically arranged coating and developing unit blocks, including a buffer module capable of holding more substrates than the wet processing modules, and a controller that manages substrate carrying to absorb rate differences and inhibit substrate flow when necessary, reducing the number of carrying arms and system footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the exposure system operates at a lower processing rate than the coating and developing system, then the exposure quality can be maintained, but the coating and developing system experiences idle time and reduced productivity
Solution Approach 1:
The buffer module stores substrates that have completed coating and developing processes before they are needed by the exposure system. This preliminary storage allows the coating and developing system to operate continuously at its optimal speed, preparing substrates in advance for when the exposure system is ready to process them, thereby eliminating idle time and maintaining high productivity while ensuring exposure quality is not compromised
Solution Approach 2:
The buffer module acts as an intermediary between the coating and developing system and the exposure system. It decouples the two systems, allowing them to operate at different processing rates without directly affecting each other. The buffer absorbs the rate difference, enabling the coating and developing system to maintain high throughput while the exposure system operates at its optimal quality-driven pace
2Productivity
If a buffer module with large capacity is installed in the interface block, then the difference in processing rates can be absorbed, but the system footprint and manufacturing cost increase
Solution Approach 1:
The buffer module is positioned within the coating and developing system rather than in the interface block between systems. This spatial reconfiguration utilizes the available space within the coating and developing system's footprint, avoiding the need to expand the overall system area. The buffer integrates into the existing system layout, absorbing processing rate differences without requiring additional floor space or increasing manufacturing cost
3Productivity
If multiple carrying arms are installed in the interface block, then the substrate transfer capacity is increased, but the device complexity and cost increase
Solution Approach 1:
The buffer module is extracted from the interface block and integrated into the coating and developing system. This extraction eliminates the need for multiple carrying arms in the interface block, as the buffer handles the substrate storage and release functions. The carrying mechanism is simplified to a single arm that transfers substrates between the buffer and the exposure system, reducing device complexity and cost while maintaining adequate transfer capacity
Data Source
AI summary
A buffer module is installed in a coating film forming unit block of a coating and developing system to reduce the number of interface arms needed by an interface block, and the manufacturing cost and footprint of the coating and developing system. For example, buffer modules BF31 to BF34 capable of holding a number of wafers W greater by one than the number of coating modules COT1 to COT3 of a COT layer B3 is installed in the COT layer B3, In the COT layer B3, a wafer W is carried along a carrying route passing a temperature control module CPL3, COT1 to COT3, a heating and cooling module LHP3, and the buffer modules BF31 to BF34. A main arm A3 carries wafers W such that the number of wafers W placed in the modules on the downstream side of the CPL3 is greater by one than the number of modules between the CPL3 and the buffer module when a processing rate at which an exposure system processes wafers W is lower that at which the COT layer B3 processes wafers W.