Buffered Memory Control for PCM Write Latency
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Solution Overview
Problem
Phase Change Memory (PCM) devices face limitations when used as RAM replacements due to restricted operation during write and read operations, requiring additional mechanisms and status checks, as they cannot perform read operations during write operations and write operations are slower, necessitating suspension for read access.
Innovation Solution
A memory system architecture that includes a host and memory coupled by command and data buses, with a buffer managing operations through a variable latency period, allowing for controlled write and read operations by managing cache lines and providing data through a flush command to ensure timely completion of operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If PCM is used to implement random access memory, then non-volatile memory capability is achieved, but write operations become slower and require additional management time
Solution Approach 1:
A buffer is introduced as an intermediary component between the host and the PCM memory array. The buffer temporarily stores data during write operations, allowing the host to continue issuing commands without waiting for the slow PCM write completion. This mediator absorbs the speed mismatch between fast host interfaces and slow PCM writes, enabling non-volatile storage capability while maintaining system throughput.
Solution Approach 2:
Data is preliminarily stored in the buffer before being written to the PCM memory array. This preliminary action allows the system to accept write commands quickly and prepare data for eventual PCM writing, decoupling the host's write operations from the actual PCM programming timing. The buffer holds data in advance, enabling faster apparent write speeds from the host perspective.
2Ease of operation
If read operations are performed during write operations on PCM, then operational flexibility is reduced, but status registers must be regularly queried and write operations may need to be suspended
Solution Approach 1:
The buffer acts as a mediator that isolates the host from the complex state management of PCM operations. While data is being prepared in or transferred through the buffer, the host can issue read commands without needing to query status registers or determine write completion states. The buffer absorbs the complexity of coordinating read/write timing, allowing simpler host operation.
Solution Approach 2:
The memory system is segmented into distinct functional components: the buffer for temporary data storage and the PCM array for persistent storage. This segmentation allows independent management of read and write operations in different parts of the system. The buffer handles data preparation and temporary storage, while the PCM array handles persistent storage, allowing reads to proceed from buffered data without suspending write operations to the array.
3Ease of operation
If write operations are suspended for read access requests, then read access is enabled, but operational efficiency decreases
Solution Approach 1:
The system segments data into buffered data and array-stored data. Reads can be served from the buffer without affecting writes to the PCM array, enabling concurrent operations. This segmentation creates parallel operation paths where the buffer handles read requests while the array continues write operations, maintaining productivity while enabling read access.
Solution Approach 2:
The buffer serves as an intermediary that fulfills read requests without requiring suspension of write operations to the PCM array. Data can be read from the buffer while writes continue to be queued or executed in the array, eliminating the need to suspend operations. The buffer mediates between read and write demands, maintaining operational efficiency by preventing write suspensions.
Data Source
AI summary
Apparatuses and methods for providing data from a buffer are disclosed herein. An example apparatus may include an array, a buffer, and a memory control unit. The buffer may be coupled to the array and configured to store data. The memory control unit may be coupled to the array and the buffer. The memory control unit may be configured to cause the buffer to store the data responsive, at least in part, to a first write command and may further be configured to cause the buffer to store the data in the array responsive, at least in part, to a flush command. The memory control unit may further be configured to interrupt the flush command to prepare for a read command or a second write command and resume the flush command once the read command or the second write command is performed.