Resettable Buffer Circuit to Prevent Clock Phase Reversal
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Solution Overview
Problem
As the frequency of clock signals increases, semiconductor apparatuses face issues with buffer circuits generating output signals with opposite phases during transitions from deactivation to activation periods, leading to quasi-steady states and reduced amplification efficiency.
Innovation Solution
The proposed buffer circuit includes an amplifying circuit, a latch circuit, and variable loads that adjust current based on a reset signal, ensuring voltage levels are maintained and amplified correctly across output nodes, even during reset periods, to prevent phase reversals and enhance operational stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the buffer circuit is reset during deactivation period, then power consumption is reduced, but voltage levels of input and output signals become undefined causing phase reversal upon activation
Solution Approach 1:
The patent applies preliminary action by setting specific voltage levels for first and second nodes before the buffer circuit enters activation mode. The control circuit pre-charges or pre-discharges these nodes to predetermined voltage levels during deactivation period, ensuring that when activation begins, the amplifying circuit starts from a known stable state rather than an undefined reset state, thereby preventing phase reversal while maintaining power efficiency.
Solution Approach 2:
The patent utilizes parameter changes by dynamically adjusting the voltage levels of first and second nodes based on the operational state of the buffer circuit. The control circuit monitors activation/deactivation status and modifies voltage parameters accordingly - maintaining defined voltage levels during activation for proper signal amplification, and controlling voltage levels during deactivation to minimize power consumption while avoiding undefined states that cause phase reversal.
2Speed
If the frequency of clock signal increases, then operating speed of semiconductor apparatus increases, but the buffer circuit generates output signals with opposite phase and operates in quasi-steady state
Solution Approach 1:
The patent applies preliminary action by preparing the voltage levels of first and second nodes in advance before high-frequency clock signals arrive. The control circuit ensures nodes are pre-charged or pre-discharged to correct voltage levels during deactivation periods between clock cycles, allowing the amplifying circuit to immediately respond to incoming clock edges without entering quasi-steady state, thereby maintaining signal amplification accuracy even at high operating frequencies.
Solution Approach 2:
The patent utilizes dynamics by making the voltage levels of first and second nodes dynamically adjustable based on real-time operational conditions. The control circuit continuously adapts voltage parameters in response to clock signal frequency and buffer circuit state, enabling the circuit to maintain proper phase relationships and avoid quasi-steady state operation even when clock frequency increases, thus preserving signal amplification accuracy at high speeds.
Data Source
AI summary
A buffer circuit may include: an amplifying circuit configured to change, based on a first input signal and a second input signal, voltage levels of a first output node and a second output node in a range between a first power voltage and a second power voltage; a latch circuit configured to latch the voltage levels of the first output node and the second output node; a first variable load configured to adjust, based on a reset signal, an amount of current provided by a first power voltage terminal at the first power voltage to the first output node; a second variable load configured to adjust, based on the reset signal, an amount of current provided by the first power voltage terminal to the second output node; and a reset circuit configured to drive the first output node to the second power voltage based on the reset signal.