Buffer Plug in Through-Silicon Vias for Chip Package Delamination
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Solution Overview
Problem
Through-silicon vias in chip packages are prone to delamination during thermal cycle tests, reducing the reliability of packaged chips due to the separation of the redistribution layer from the sidewall of the vias.
Innovation Solution
A chip package design featuring a semiconductor substrate with through holes, a conductive trace layer, a buffer plug, and a protection layer, where the buffer plug is partially cured to reduce adhesion and deform under thermal stress, and the buffer plug's coefficient of thermal expansion is adjusted to match the difference between the protection and insulating layers, preventing delamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If through-silicon vias are used to reduce chip package size, then the chip package size is reduced, but the redistribution layer delaminates from the sidewall of the vias during thermal cycle tests
Solution Approach 1:
A buffer plug is introduced as an intermediary component between the conductive trace layer (redistribution layer) and the protection layer within the through-silicon via. This buffer plug mediates the interaction between these layers during thermal cycling, absorbing expansion differences and preventing direct delamination between the redistribution layer and via sidewall, thus resolving the contradiction between via functionality and reliability.
Solution Approach 2:
The buffer plug's coefficient of thermal expansion is specifically adjusted to match the difference between the protection layer and insulating layer. By changing this physical parameter, the buffer plug compensates for thermal expansion mismatches during thermal cycling, preventing delamination while maintaining the via's size-reduction function.
2Reliability
If the buffer plug is designed to deform under thermal stress, then delamination is prevented, but the structural integrity may be compromised
Solution Approach 1:
The buffer plug is positioned locally within the through-silicon via, specifically between the conductive trace layer and protection layer. Its material properties are optimized for local stress absorption and deformation under thermal stress, while the overall structural integrity is maintained by the rigid semiconductor substrate and via structure. This localized approach prevents delamination without compromising global structural strength.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances the reliability of chip packages by preventing delamination during thermal cycles and maintaining electrical connectivity, while also providing a hermetic seal and moisture resistance.
Implementation Method 1
the buffer plug's coefficient of thermal expansion is adjusted to match the difference between the protection and insulating layers, preventing delamination
Implementation Method 2
A conductive trace layer is conformally formed over the first surface and extends to the through holes
Data Source
AI summary
A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate, having a first surface and an opposite second surface. A through hole is formed on the first surface, extending from the first surface to the second surface. A conductive trace layer is formed on the first surface and in the through hole. A buffer plug is formed in the through hole and a protection layer is formed over the first surface and in the through hole.