Buffer Backup Cache Replaces Failed Memory Cells

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Solution Overview

Problem

Memory cells in computer systems can fail over time, leading to errors and performance issues, requiring costly repairs as large blocks of memory are taken out of memory maps, resulting in system downtime and inefficiency.

Innovation Solution

A buffer system with a backup cache and error data queue is implemented to replace failed memory cells by transferring data from the backup cache to the error data queue, allowing the buffer controller to redirect data access, thereby maintaining system performance without immediate repair.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If memory cells are used to store data over long periods, then data storage capacity is maintained, but memory cells fail over time causing errors and requiring system downtime for repairs

Engineering Contradiction:
Improvememory cell reliabilityVSAvoidsystem downtime
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent implements a buffer that proactively detects failed memory cells and replaces them with alternative storage locations (such as solid-state memory or different memory regions) before the failures cause system errors or downtime. This preliminary replacement action prevents the worsening of reliability issues and eliminates the need for reactive system shutdowns and repairs.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If failed memory cells are detected and large blocks of memory are taken out of memory maps, then data integrity is maintained, but available memory capacity decreases and performance issues occur

Engineering Contradiction:
Improvedata integrityVSAvoidsystem performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent creates redundant copies of data in alternative storage locations within the buffer (such as solid-state memory devices or different memory regions). When memory cells fail, these pre-existing copies can immediately replace the failed data without taking large blocks of memory out of service, thus maintaining both data integrity and system performance by keeping memory capacity available.

Inventive Principle:
Principle #26Copying

3Productivity

If memory cells continue to be used despite failures, then memory capacity is maximized, but errors increase and system reliability deteriorates

Engineering Contradiction:
Improvememory capacity utilizationVSAvoidsystem reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent implements a feedback mechanism where the buffer continuously monitors memory cell health and performance metrics. When failures are detected, the system automatically replaces failed cells with alternative storage locations and updates memory maps accordingly. This closed-loop feedback allows the system to maintain high memory capacity utilization while preventing reliability deterioration through automatic error correction and replacement.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS9128887B2Using a buffer to replace failed memory cells in a memory component
Publication Date: 2015.09.08 LENOVO GLOBAL TECHNOLOGIES SWITZERLAND INTERNATIONAL GMBH
  • US9128887B2 patent drawing
  • US9128887B2 patent drawing
  • US9128887B2 patent drawing

AI summary

Methods and data processing systems for using a buffer to replace failed memory cells in a memory component are provided. Embodiments include determining that a first copy of data stored within a plurality of memory cells of a memory component contains one or more errors; in response to determining that the first copy contains one or more errors, determining whether a backup cache within the buffer contains a second copy of the data; and in response to determining that the backup cache contains the second copy of the data, transferring the second copy from the backup cache to a location within an error data queue (EDQ) within the buffer and updating the buffer controller to use the location within the EDQ instead of the plurality of memory cells within the memory component.