Buffer Segmentation for Deadlock Prevention in Multi-Core Communication

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Solution Overview

Problem

Communication between integrated processor circuits in computing systems often leads to deadlocks due to insufficient buffer capacity for handling synchronization and write messages, causing channels to become blocked and preventing forward progress.

Innovation Solution

Incorporating buffers in each integrated circuit with additional slots to reserve space for guaranteed forward progress, ensuring that communication channels can handle a maximum number of outstanding synchronization messages without overflowing, thereby preventing deadlocks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If buffer capacity is increased to handle more outstanding messages, then deadlock prevention is improved, but device complexity and resource consumption increase

Engineering Contradiction:
Improvedeadlock preventionVSAvoidbuffer capacity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The buffer is segmented into different message types (synchronization messages and write messages) with separate tracking mechanisms. This allows the system to manage different message categories independently, preventing deadlocks related to synchronization messages while maintaining efficient handling of write messages, thus avoiding the need for a monolithic large buffer.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system changes the parameter of message tracking by introducing a counter that monitors the number of outstanding synchronization messages. When this counter reaches a threshold, the system adjusts buffer allocation and message handling parameters dynamically, allowing flexible buffer management that prevents deadlocks without requiring excessive fixed buffer capacity.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If buffer slots are reserved for synchronization messages to prevent deadlocks, then forward progress is guaranteed, but the ability to handle write messages may be restricted

Engineering Contradiction:
Improveforward progressVSAvoidmessage handling flexibility
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The buffer is segmented into different message types (synchronization messages and write messages) with separate tracking mechanisms. This allows the system to manage different message categories independently, preventing deadlocks related to synchronization messages while maintaining efficient handling of write messages, thus avoiding the need for a monolithic large buffer.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system reserves only a portion of the buffer for synchronization messages based on the actual number of outstanding synchronization operations, rather than reserving the entire buffer. This partial reservation ensures forward progress for synchronization messages while leaving sufficient space for write messages, achieving a balance between deadlock prevention and message handling flexibility.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS9870328B2Managing buffered communication between cores
Publication Date: 2018.01.16 MARVELL ASIA PTE LTD
  • US9870328B2 patent drawing
  • US9870328B2 patent drawing
  • US9870328B2 patent drawing

AI summary

Communicating among multiple sets of multiples cores includes: buffering messages in first buffer associated with a first set of multiple cores; buffering messages in a second buffer associated with a second set of multiple cores; and transferring messages over communication circuitry from cores not in the first set to the first buffer, and to transferring messages from cores not in the second set to the second buffer. A first core of the first set sends messages corresponding to multiple types of instructions to a second core of the second set through the communication circuitry. The second buffer is large enough to store a maximum number of instructions of a second type that are allowed to be outstanding from cores in the first set at the same time, and still have enough storage space for one or more instructions of a first type.