Buffer Circuit Slew Rate Compensation for Low-Power DDICs
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Solution Overview
Problem
Display driver integrated circuits (DDICs) face challenges in achieving high resolution and low power consumption due to the need for improved slew rate in buffer amplifiers, which are constrained by size and power consumption requirements.
Innovation Solution
A buffer circuit design that includes an input stage, load stage, output stage, and slew rate compensator, utilizing comparators, source and sink current circuits, and current mirror structures to regulate gate voltages and improve slew rate, allowing the output voltage to quickly follow input voltage transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the slew rate of the buffer amplifier is improved to satisfy high resolution time-division driving, then the data output speed increases, but the size and power consumption of the DDIC increase
Solution Approach 1:
The patent implements dynamic current control by switching between first and second current values based on the transition direction (rising or falling) of the input signal. The slew rate compensator dynamically adjusts the current supplied to the load stage, providing higher current during transitions to boost slew rate while maintaining lower current during steady states to reduce power consumption.
Solution Approach 2:
The patent changes the current parameter dynamically by switching between different current values (first current value and second current value) based on signal transition conditions. This parameter change allows the circuit to optimize between speed (during transitions) and power consumption (during steady states), resolving the contradiction between slew rate improvement and power consumption reduction.
2Speed
If the slew rate of the buffer amplifier is improved to satisfy high resolution time-division driving, then the data output speed increases, but the size of the DDIC increases
Solution Approach 1:
The patent uses dynamic switching between different current modes to achieve high slew rate only when needed (during signal transitions). This dynamic approach allows the use of smaller, more compact circuit components compared to traditional designs that would require continuously high current capability, thus reducing overall DDIC size while maintaining the required speed performance.
3Productivity
If time-division driving is used to increase resolution with a single buffer amplifier, then the number of components is reduced, but the time available for data output is reduced requiring higher slew rate
Solution Approach 1:
The slew rate compensator detects upcoming transitions and prepares the circuit by switching to higher current mode before the actual data output transition occurs. This preliminary action ensures that when the data output transition is needed, the circuit is already configured to provide the necessary current for fast slew rate, effectively compensating for the reduced time available in time-division driving.
Solution Approach 2:
The patent employs feedback mechanisms where the slew rate compensator monitors the input signal and adjusts the current supply accordingly. This feedback control allows the circuit to respond to transition requirements in real-time, ensuring adequate slew rate is provided during the limited data output time windows of time-division driving, thereby maintaining high productivity despite reduced time availability.
Data Source
AI summary
A buffer circuit for generating an output voltage according to an input voltage includes: an input stage configured to provide a first differential current to a load stage or receive a second differential current from the load stage based on a difference between the input voltage and the output voltage; the load stage configured to apply gate voltages to a first output transistor and a second output transistor of an output stage based on the first differential current or the second differential current; the output stage configured to regulate the output voltage based on the gate voltages applied to the first output transistor and the second output transistor; and a slew rate compensator configured to provide a source current to the load stage or receive a sink current from the load stage to regulate the gate voltages of the first output transistor and the second output transistor.