Buffer Output Stage Slew Acceleration for High-Capacitance Displays
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Solution Overview
Problem
As display devices become larger and have higher resolutions, the reduced horizontal period and increased load capacitance lead to a deterioration in image quality due to the inability of the source drive signal to reach the target voltage within the predetermined period, and existing methods to improve slew rate require increased power consumption.
Innovation Solution
A slew rate acceleration circuit is configured to detect the current flowing through the load stage of the buffer circuit, compare it with a reference value, and supply an adjusting driving voltage to the output stage to increase the slew rate without increasing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the bias current of the buffer circuit is increased to improve the slew rate, then the slew rate is improved, but the power consumption increases
Solution Approach 1:
The patent applies dynamics by making the bias current adjustable rather than fixed. The bias current is dynamically changed based on the operating conditions of the buffer circuit, allowing the slew rate to be improved when needed while maintaining lower power consumption during normal operation. This is achieved through a control circuit that adjusts the bias current in response to detected signal conditions.
Solution Approach 2:
The patent changes the bias current parameter dynamically based on operating conditions. By monitoring the output signal characteristics and adjusting the bias current accordingly, the system achieves high slew rate when required while minimizing power consumption during steady-state operation, thus resolving the contradiction between speed and energy usage.
2Manufacturing precision
If the display device size and resolution are increased, then the image quality is improved, but the horizontal period is reduced and load capacitance increases causing the source drive signal to fail to reach target voltage
Solution Approach 1:
The patent employs feedback by detecting the output signal characteristics of the buffer circuit and using this information to adjust the bias current. The control circuit continuously monitors the signal conditions and modifies the bias current to ensure the source drive signal reaches the target voltage within the reduced horizontal period, thereby maintaining image quality despite increased load capacitance.
Solution Approach 2:
The system dynamically adjusts the bias current based on real-time signal conditions detected from the output. This dynamic adaptation allows the buffer circuit to compensate for the increased load capacitance and reduced horizontal period, ensuring the source drive signal achieves the required voltage level within the constrained time frame for high-resolution displays.
Data Source
AI summary
A slew rate acceleration circuit in a buffer circuit, is configured at least to detect a current flowing through a load stage of the buffer circuit, compare a value of the detected current with a reference value, and supply an adjusting driving voltage to an output stage of the buffer circuit based on results of the comparison for increasing a slew rate of the buffer circuit.