Buffer Circuit Slew Compensation With Offset Blocking
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Solution Overview
Problem
Display driver integrated circuits (DDICs) face challenges in improving slew rate, reducing size, and lowering power consumption, especially during time-division driving of R/G/B pixels, which can lead to overshoot, undershoot, and DC offset issues due to noise from slew rate compensation circuits.
Innovation Solution
A buffer circuit design that includes an input stage, a load stage, and an output stage, along with a slew rate compensation circuit and an offset blocking circuit. The slew rate compensation circuit provides compensation currents based on voltage differences between input and output voltages, while the offset blocking circuit uses offset control signals to turn off the current source of the slew rate compensation circuit during normal states, preventing noise and overshoot/undershoot.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a slew rate compensation circuit is added to improve the slew rate, then the slew rate performance is improved, but overshoot and undershoot occur in transient response state
Solution Approach 1:
The offset control signal output stage generates control signals in advance to predict when overshoot or undershoot may occur during transient response. The offset blocking circuit uses these advance signals to preemptively block the compensation current, preventing the harmful overshoot/undershoot before it occurs, while still allowing the compensation circuit to improve slew rate during normal operation.
2Speed
If a slew rate compensation circuit is added to improve the slew rate, then the slew rate performance is improved, but DC offset problems occur due to noise from the compensation circuit
Solution Approach 1:
The offset blocking circuit dynamically controls the compensation current based on real-time operating conditions. By using the offset control signal output stage to generate dynamic control signals, the system adapts the compensation current blocking status according to whether the circuit is in transient response state or normal operation, thereby eliminating DC offset and noise while preserving slew rate improvement when needed.
3Manufacturing precision
If buffer amplifiers are configured for each R/G/B pixel to satisfy high resolution, then the display quality is improved, but the size and power consumption of the DDIC increase greatly
Solution Approach 1:
The buffer amplifier circuit is designed with multi-functionality to serve multiple purposes. The same buffer circuit can handle different pixel types (R/G/B) and different operating modes (time-division driving vs. dedicated buffering) by configuring the offset blocking circuit and compensation circuit appropriately. This universality allows one buffer circuit design to replace multiple dedicated buffer circuits, reducing overall DDIC size while maintaining high resolution capability.
4Manufacturing precision
If buffer amplifiers are configured for each R/G/B pixel to satisfy high resolution, then the display quality is improved, but the power consumption of the DDIC increases greatly
Solution Approach 1:
The offset blocking circuit operates periodically based on the driving mode. During time-division driving, the compensation circuit is blocked during periods when it would generate harmful effects, and activated only when needed for slew rate improvement. This periodic control reduces average power consumption compared to having the compensation circuit continuously active, while still achieving high resolution display quality when required.
Data Source
AI summary
A buffer circuit includes an input stage configured to provide a differential current to a load stage or receive the differential current from the load stage based on a difference between an input voltage and an output voltage, wherein the load stage is configured to apply gate voltages to first and second output transistors of an output stage, and wherein the output stage is configured to regulate the output voltage; a slew rate compensation circuit configured to provide a slew rate compensation current to the load stage or receive the slew rate compensation current from the load stage; an offset control signal output stage configured to output an offset control signal by being applied with first and second N-bit control signals; and an offset blocking circuit comprising a switch configured to turn off a current source of the slew rate compensation circuit by the offset control signal.