Buffer Material and Stiffener for Semiconductor Wafer Warpage
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Solution Overview
Problem
Three-dimensional integrated circuit devices face issues such as wafer warpage, mechanical failure, delamination, thermo-mechanical failure, and thermal expansion mismatch leading to device failures and increased costs during the fabrication and singulation of semiconductor devices with through-silicon vias and thin silicon chip-to-wafer bonding.
Innovation Solution
The implementation of a semiconductor device structure that includes a buffer material between the semiconductor wafer and adhesive layer, an underfill layer with a coefficient of thermal expansion matched to the buffer material, and a stiffener layer to prevent wafer warpage and thermal stress, along with the removal of oxide on dicing streets to prevent delamination, and the use of an ultra-thin semiconductor wafer with metallization and vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If through-silicon vias and thin silicon chip-to-wafer bonding are used to achieve compact three-dimensional integrated circuit devices, then device functionality and integration density are improved, but wafer warpage and mechanical failure occur during fabrication and handling
Solution Approach 1:
A buffer material layer is introduced between the thin silicon wafer and the adhesive layer to act as a mechanical intermediary. This buffer layer absorbs and distributes thermal and mechanical stresses, preventing direct stress transmission that would cause wafer warpage and bonding failure, thereby enabling reliable handling of ultra-thin wafers with through-silicon vias
Solution Approach 2:
The patent employs a composite structure consisting of multiple layers with different material properties: the thin silicon wafer, buffer material, adhesive layer, and stiffener layer. Each layer is selected for its specific mechanical and thermal properties to collectively manage stress, prevent warpage, and maintain structural integrity during fabrication and operation
2Adaptability or versatility
If dissimilar materials with different coefficients of thermal expansion are used in the device structure, then device functionality is improved, but thermal expansion mismatch causes delamination and device failure
Solution Approach 1:
The buffer material is specifically selected and engineered to have a coefficient of thermal expansion that matches or is compatible with the adjacent layers (thin silicon wafer and adhesive layer). By controlling this critical thermal parameter, the patent prevents thermal stress accumulation and delamination that would otherwise occur due to mismatched thermal expansion coefficients of dissimilar materials
Solution Approach 2:
Different regions of the device structure are assigned different material properties tailored to their specific functional requirements. The buffer material layer is specifically designed with thermal expansion properties matched to the wafer, while other layers have properties optimized for their respective functions, creating a locally optimized structure that prevents delamination
3Reliability
If oxide is removed from dicing streets to prevent delamination, then bonding reliability is improved, but additional processing steps are required
Solution Approach 1:
The oxide removal from dicing streets is performed as a preliminary processing step before the bonding and dicing operations. By removing oxide in advance, the patent ensures that the bonding surfaces are clean and free from contaminants that would cause delamination, preventing future reliability issues before they occur
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces wafer warpage, mechanical failure, and thermal stress, enhancing the yield and reliability of semiconductor devices by matching thermal expansion coefficients and providing structural support, thereby reducing the cost and improving the handling and packaging of three-dimensional integrated circuit devices.
Implementation Method 1
an underfill layer with a coefficient of thermal expansion (CTE) matched to the CTE of the buffer material
Implementation Method 2
a buffer material between the semiconductor wafer and adhesive layer
Implementation Method 3
a stiffener layer to prevent wafer warpage and thermal stress
Data Source
AI summary
Semiconductor devices are described that include a semiconductor device having multiple, stacked die on a substrate (e.g., a semiconductor wafer). In one or more implementations, wafer-level package devices that employ example techniques in accordance with the present disclosure include an ultra-thin semiconductor wafer with metallization and vias formed in the wafer and an oxide layer on the surface of the wafer, an integrated circuit chip placed on the semiconductor wafer, an underfill layer between the integrated circuit chip and the semiconductor wafer, a buffer material formed on the semiconductor wafer, the underfill layer, and at least one side of the integrated circuit chip, an adhesive layer placed on the buffer layer and the integrated circuit chip, and a stiffener layer placed on the adhesive layer. The semiconductor device may then be segmented into individual semiconductor chip packages.