Buffer Structure for Thermal Stress Compensation in 3D IC
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Three-dimensional integrated circuit designs face stress issues between through-silicon vias and semiconductor dies due to mismatched coefficients of thermal expansion, affecting performance and increasing manufacturing costs.
Innovation Solution
A method of forming a semiconductor structure involves bonding substrates with a buffer structure surrounded by a metal layer, which compensates for thermal expansion mismatch, and includes forming a barrier structure and passivation layers to enhance stress compensation and reduce material usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If through-silicon vias are used for chip-to-chip electrical connections in 3D IC design, then interconnection complexity and overall dimensions are reduced, but stress problems occur between the through silicon vias and the semiconductor dies due to mismatched coefficients of thermal expansion
Solution Approach 1:
A buffer structure is introduced as an intermediary layer between the metal layer (through-silicon via) and the second substrate (semiconductor die). This buffer structure has a coefficient of thermal expansion that is intermediate between the metal and the semiconductor substrate, thereby reducing the stress caused by thermal expansion mismatch. The buffer structure acts as a stress-absorbing intermediary that prevents direct stress transmission between the metal layer and the semiconductor die.
Solution Approach 2:
The patent changes the physical parameter (coefficient of thermal expansion) of the interface structure by introducing a buffer material with different thermal expansion properties. The buffer structure's coefficient of thermal expansion is specifically selected to be between that of the metal layer and the semiconductor substrate, thereby modifying the thermal-mechanical parameters of the overall structure to reduce stress.
2Stress or pressure
If a buffer structure is formed over the metal layer to compensate stress, then stress compensation is achieved, but the manufacturing process becomes more complex
Solution Approach 1:
The buffer structure is formed preliminarily during the manufacturing process, specifically after forming the metal layer and before forming the final barrier structure. By incorporating the buffer structure formation into the existing manufacturing sequence as an additional step, stress compensation is achieved without requiring a complete redesign of the manufacturing process. The buffer structure is prepared in advance to prevent stress issues before they affect the final device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method improves the performance of semiconductor structures by balancing thermal expansion and reducing manufacturing costs through effective stress compensation and material optimization.
Implementation Method 1
stress issues between through-silicon vias and semiconductor dies due to mismatched coefficients of thermal expansion
Data Source
AI summary
A method of forming a semiconductor structure includes following steps. A first substrate and a second substrate are bonded together, in which the first substrate has a landing pad. The second substrate is etched to form an opening, in which the landing pad is exposed through the opening. A metal layer is formed over the landing pad and a sidewall of the second substrate that surrounds the opening. A buffer structure is formed over the metal layer. The buffer structure is etched such that a top surface of the buffer structure is below a top surface of the metal layer. A barrier structure is formed over metal layer and the buffer structure.