Two-Phase Buffer Circuit Switching for Faster Output Fall Time
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Solution Overview
Problem
Buffer circuits in active-matrix display devices face challenges in shortening output signal fall time while reducing circuit area and power consumption, as increasing the driving performance of transistors to achieve faster fall times leads to increased leak current and higher power consumption.
Innovation Solution
A buffer circuit driving method that utilizes two transistors connected in series, where the first transistor switches during a period of a first voltage and both transistors switch during a period of a second voltage, allowing the output signal to drop without increasing circuit area or power consumption, with the second voltage being lower than the first voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the driving performance of transistors is increased to achieve faster fall times, then the output signal fall time is shortened, but the leak current increases and power consumption increases
Solution Approach 1:
The patent divides the transistor switching operation into two distinct phases: a first period where only the first transistor switches to conductive state, and a second period where both first and second transistors switch to conductive state. This segmentation allows the output signal to be discharged through two parallel paths simultaneously, achieving faster fall time without requiring a single oversized transistor that would increase leakage current and power consumption.
2Speed
If the driving performance of transistors is increased to achieve faster fall times, then the output signal fall time is shortened, but the circuit area increases
Solution Approach 1:
The patent segments the discharge function into two separate transistors operating in coordinated phases. The first transistor handles discharge during the first period, and the second transistor provides an additional discharge path during the second period. This segmentation allows each transistor to be smaller than a single transistor would need to be to achieve the same fall time, thereby reducing total circuit area.
Data Source
AI summary
A buffer circuit driving method for driving a buffer circuit including: an output terminal; a first transistor connected to a signal source of a clock signal that is of at least a first voltage or a second voltage lower than the first voltage, for supplying the first voltage to the output terminal; and a second transistor connected to a voltage source that supplies a third voltage lower than the first voltage, for supplying the third voltage to the output terminal, includes: causing the first transistor to switch to a conducting state in a period where the clock signal is of the first voltage; and causing the first transistor and the second transistor to switch to the conducting state in a period where the clock signal is of the second voltage, following the period where the clock signal is of the first voltage.