Open-Loop Buffer Circuit With Threshold Voltage Cancellation

The patent changes the electrical parameters of the transistor gates by introducing complementary transistors with opposite threshold voltage characteristics. NMOS and PMOS transistors are paired such that their threshold voltage drops and rises with temperature respectively, creating parameter cancellation effects that eliminate DC offset and temperature-dependent offsets while maintaining high input impedance and low output impedance.

The buffer circuit employs a composite transistor structure combining NMOS and PMOS transistors in complementary pairs. This composite approach leverages the opposite temperature coefficients of the two transistor types - NMOS threshold voltage decreases with temperature while PMOS increases, creating a composite effect that cancels threshold voltage mismatches and eliminates DC offset voltages.

The buffer circuit is segmented into multiple functional blocks: input stage with NMOS/PMOS complementary pairs, intermediate stages with current mirrors, and output stages with additional complementary transistor pairs. Each segment performs a specific function in the threshold voltage cancellation process, allowing systematic elimination of DC offset and temperature drift through modular complementary transistor configurations.

The circuit employs implicit feedback mechanisms where the complementary transistor pairs automatically adjust their operating points based on temperature variations. The current mirror circuits provide current feedback that ensures the threshold voltage drops in NMOS transistors are compensated by threshold voltage rises in PMOS transistors, maintaining voltage accuracy without requiring external feedback components.