Buffered Multi-Addend Adder Circuit for Precise Stochastic Computing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Stochastic computing multi-addend adder circuits face significant computing errors and reduced precision due to stochastic selection on input bitstreams with a 50% probability, leading to inaccuracies in bitstream representation and addition processes.
Innovation Solution
The implementation of a multi-addend adder circuit with a buffer circuit and computing circuit that stores and processes input data across cycles, using a scale-down coefficient to manage bitstream summation and division, thereby reducing computing errors and enhancing precision by utilizing a buffer to store and reuse data for subsequent cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If stochastic selection is performed on input bitstreams with a 50% probability using a two-input adder circuit, then the multi-addend addition can be implemented through a simple tree structure, but computing precision deteriorates due to large computing errors
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing selection probabilities in a lookup table before the actual addition operation. Instead of performing stochastic selection with 50% probability during the addition process, the system pre-computes the appropriate selection probabilities based on the input bitstreams and stores them for later use. This pre-computation eliminates the need for random selection during execution, thereby maintaining circuit simplicity while significantly improving computing precision.
Solution Approach 2:
The patent introduces a lookup table as an intermediary component between the input bitstreams and the adder circuit. This lookup table stores pre-computed selection probabilities and acts as a mediator that translates input bitstream values into deterministic selection signals. By introducing this intermediary, the system replaces the stochastic selection mechanism with a deterministic lookup-based approach, thereby eliminating computing errors while maintaining the simplicity of the tree structure.
2Ease of manufacture
If a tree structure of two-input adder circuits is used to perform multi-addend addition, then the circuit implementation is simplified, but computing precision deteriorates due to accumulation of errors from multiple stochastic selections
Solution Approach 1:
The patent extracts the error-prone stochastic selection operation from the adder circuit tree and relocates it to a pre-computation phase. By separating the selection probability calculation from the actual addition process, the system can use a simple tree structure for addition while eliminating the accumulation of stochastic errors. The extraction of the stochastic element and its replacement with deterministic lookup-based selection resolves the contradiction between circuit simplicity and computing precision.
Solution Approach 2:
The patent applies preliminary action by pre-computing all necessary selection probabilities before the addition operation begins. The lookup table is populated with pre-calculated values that encode the optimal selection probabilities for all possible input combinations. This pre-computation eliminates the need for repeated stochastic selections during the tree-based addition process, thereby preventing error accumulation while maintaining the ease of circuit implementation.
3Productivity
If stochastic selection with 50% probability is used in each stage of the adder tree, then the addition operation can be performed efficiently, but computing precision deteriorates due to loss of information in bitstream representation
Solution Approach 1:
The patent introduces a lookup table as an intermediary that preserves bitstream representation accuracy. Instead of performing lossy stochastic selection at each stage, the lookup table stores pre-computed selection probabilities that exactly represent the intended addition operation. This intermediary structure allows the system to maintain full information fidelity throughout the computation process while still achieving efficient addition operation through the streamlined lookup-based approach.
Solution Approach 2:
The patent replaces the mechanical stochastic selection process with a deterministic lookup-based system. The random selection mechanism, which inherently loses information due to its probabilistic nature, is substituted with a deterministic lookup table that provides exact selection signals. This substitution eliminates information loss while maintaining the efficiency of the addition operation, as the lookup process is computationally inexpensive and can be executed rapidly.
Data Source
AI summary
A multi-addend adder circuit used for multi-addend addition in a polar representation in stochastic computing. The multi-addend adder circuit includes a buffer circuit and a computing circuit, where the buffer circuit is configured to store to-be-buffered data for at least one cycle and output buffer data, and the computing circuit is configured to process a plurality of pieces of bitstream data and the buffer data and output one piece of bitstream data and the to-be-buffered data, where the piece of output bitstream data is a quotient of dividing a sum of summation data and the buffer data by a scale-down coefficient, the output to-be-buffered data is a remainder of dividing a sum of all summation data until a current cycle by the scale-down coefficient, and the summation data is a quantity of bits whose values are 1 in the plurality of pieces of first bitstream data.