Buffered Conduits for SOC Crosstalk and Timing
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Solution Overview
Problem
In system on a chip (SOC) integrated circuits, the determination of connections between modules often results in increased die size and manufacturing cost due to adverse cross-talk between bus connections, which complicates timing issues and reduces predictability in timing closure.
Innovation Solution
The implementation of a custom-buffered bus channel using non-default direction routing, three-dimensional wire spacing, and shielding, along with criticality-dependent lane re-assignment and on-route buffering, to reduce cross-talk and enhance timing predictability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional bus routing is used to connect modules in SOC, then connections are established, but die size increases and manufacturing cost increases due to adverse cross-talk
Solution Approach 1:
The patent transitions from two-dimensional planar routing to three-dimensional routing by utilizing multiple metal layers and vertical vias. This allows bus connections to route through the third dimension (layer depth), reducing lateral spacing requirements and enabling tighter channel implementation that decreases die area while maintaining timing predictability through controlled signal paths.
Solution Approach 2:
The patent introduces buffered conduit structures as intermediary elements between source and destination modules. These buffered conduits act as controlled intermediate stages that isolate timing-critical signals from cross-talk effects, enabling predictable timing closure while allowing denser routing that reduces overall die area.
2Reliability
If conventional bus routing is used to connect modules in SOC, then connections are established, but manufacturing cost increases due to adverse cross-talk
Solution Approach 1:
By utilizing three-dimensional routing across multiple metal layers, the patent reduces the need for extensive lateral spacing and shielding that would increase die area. This dimensional transition enables more efficient space utilization, reducing manufacturing cost while maintaining timing closure predictability through controlled signal integrity.
Solution Approach 2:
The patent employs buffered conduit structures that actively control signal parameters (voltage, timing) along the transmission path. This parameter control compensates for variations in routing length and cross-talk effects, enabling predictable timing closure without requiring excessive spacing or shielding that would increase manufacturing cost.
3Productivity
If conventional bus routing is used, then connections are made, but timing issues between modules are not properly addressed
Solution Approach 1:
The patent segments long bus routes into smaller controlled segments using buffered conduit structures. Each buffered conduit represents a discrete, characterized timing segment with known propagation delays. This segmentation enables accurate timing analysis and closure while maintaining high bus throughput through optimized segment interconnections.
Solution Approach 2:
The patent performs preliminary timing characterization and buffer insertion during the routing phase rather than attempting timing closure after routing is complete. This preliminary action establishes predictable timing relationships early in the design flow, enabling faster timing closure and maintaining high productivity throughout the manufacturing process.
4Area of stationary object
If standard routing is used, then bus connections are established, but cross-talk between connections increases
Solution Approach 1:
The patent uses three-dimensional routing to separate parallel bus connections vertically across different metal layers rather than requiring large lateral spacing. This vertical separation in the third dimension reduces capacitive and inductive cross-talk between adjacent connections while enabling tighter channel implementation that increases channel density and reduces die area.
Solution Approach 2:
The patent introduces buffered conduit structures as intermediary elements that isolate adjacent bus connections. These buffered conduits act as shielding and isolation barriers that reduce cross-talk effects between neighboring connections, enabling higher channel density with controlled cross-talk levels that would not be achievable with standard routing.
Data Source
AI summary
A method of manufacturing a system on a chip and a system on a chip including a set of pre-designed modules. These modules are place on a semiconductor and connecting by a set of busses formed according to a set of design rules specifying tracks having a minimum size of conductors and a minimum spacing between conductors. The busses are routed in a preferred direction. The busses include minimum size conductors at alternate tracks within a selected metal layer of the semiconductor and minimum size conductors at alternate tracks in a different metal layer. The conductors in the different metal layer are connected to corresponding connectors in the selected metal layer by vias. Shields of conductors not connected to the bus may be included in tracks not including bus conductors.