Buffered Resistor-String DAC Architecture for Low Power LCD Driving
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Solution Overview
Problem
Existing digital-to-analog converter (DAC) architectures for small format liquid crystal display (LCD) applications face challenges with high power dissipation and poor settling time, limiting their scalability and efficiency in driving high-resolution displays.
Innovation Solution
A scalable DAC architecture with a resistor divider voltage reference and multiplexers, buffered at binary fold points to reduce output impedance and power consumption, using refresh buffers to minimize power dissipation and enhance settling time, while allowing easy expansion and gamma correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional DAC architectures are used for small format LCD displays, then the display can be driven with adequate resolution, but power dissipation becomes excessively high
Solution Approach 1:
The reference resistor string is divided into multiple segments with different resistance values. Each segment corresponds to a specific digital input code range, allowing the DAC to select appropriate resistance combinations to minimize power dissipation while maintaining the required resolution for driving LCD displays.
Solution Approach 2:
The patent employs variable resistance values in the reference resistor string segments, changing the resistance parameters dynamically based on the digital input code. This allows optimization of power dissipation across different operating ranges while maintaining adequate display resolution through selective segment activation.
2Measurement precision
If conventional DAC architectures are used for small format LCD displays, then the display can be driven with adequate resolution, but settling time becomes excessively slow
Solution Approach 1:
By segmenting the reference resistor string into multiple parallel paths with different resistance values, the DAC can quickly switch between segments based on the digital input code. This segmented architecture reduces the effective resistance seen by the output capacitor, thereby decreasing the RC time constant and improving settling time while maintaining resolution.
Solution Approach 2:
The patent implements a dynamic switching mechanism that actively selects and switches between different resistor segments based on the digital input code. This dynamic reconfiguration allows the DAC to optimize its settling characteristics for each code transition, significantly reducing worst-case settling times compared to static conventional architectures.
3Adaptability or versatility
If the DAC architecture is made scalable for higher resolutions, then it can accommodate larger displays, but device complexity increases
Solution Approach 1:
The reference resistor string is segmented into reusable units that can be replicated and combined to achieve different resolution levels. This modular segmentation allows the same basic circuit topology to be scaled from lower to higher resolutions simply by increasing the number of segments, rather than redesigning the entire architecture.
Solution Approach 2:
The patent designs the reference resistor string segments and switching circuitry to serve multiple functions across different resolution configurations. The same segment structure and control logic can be used for various bit-depth implementations, making the DAC architecture universally applicable and easily scalable without proportionally increasing complexity.
4Adaptability or versatility
If more DAC channels are added to support higher display resolutions, then the display capability is improved, but power dissipation increases
Solution Approach 1:
Multiple DAC channels share a common reference resistor string and control logic infrastructure. By merging the reference voltage generation and digital-to-analog conversion core across multiple channels, the patent reduces redundant power-consuming elements while still supporting the required number of channels for high-resolution displays.
Solution Approach 2:
The reference resistor string and control circuitry are designed to serve multiple DAC channels simultaneously. Each channel can independently utilize the shared reference structure, eliminating the need for separate power-intensive reference circuits per channel and thereby reducing total power dissipation while maintaining multi-channel capability.
Data Source
AI summary
A system and method are disclosed for providing an ultra low power scalable digital-to-analog converter architecture. Refresh buffer circuits are provided to buffer a voltage reference resistor string. The refresh buffer circuits may be coupled to the resistor string at selected binary fold points. The refresh buffer circuits can reduce the output impedance of the resistor string. Also, each digital-to-analog converter channel can be provided with a multi-dimensional multiplexer that minimizes settling time. The number of refresh buffer circuits and the number of dimensions of the multiplexer can be selected to maximize circuit performance for a given load capacitance and bit rate of the digital-to-analog converter.