Buffered-Voltage DAC Self-Calibration for Op-Amp Offset Drift

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Solution Overview

Problem

Existing buffered-voltage DACs face challenges in calibration, particularly for high power or high speed applications, as op-amp input offset is difficult to adjust for temperature and voltage dependencies, limiting their accuracy and range of operation.

Innovation Solution

A self-calibrating buffered-voltage DAC circuit that includes a voltage to frequency converter, counter, comparator, and DAC error code module to measure and correct for op-amp input offset by converting analog signals to digital frequencies, calculating a calibration offset, and applying it to the input signal, allowing for temperature and speed variations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If chopping/auto zero op-amp is used for calibration, then op-amp input offset can be corrected, but the solution is limited to sampling rates of less than around 300 ksps

Engineering Contradiction:
Improveop-amp input offset correctionVSAvoidsampling rate
Core Design Contradiction:
Measurement precisionVSSpeed

Solution Approach 1:

The patent employs dynamic element matching (DEM) technique where the DAC structure is periodically switched between different configurations at a frequency higher than the Nyquist frequency. This dynamic switching randomizes the position of mismatched components, effectively distributing the offset error across all output codes and enabling calibration to work at high sampling rates beyond the 300 ksps limitation of static calibration methods.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements periodic calibration sequences where the DAC undergoes systematic switching patterns at predetermined frequencies. These periodic actions allow the calibration circuit to measure and correct offset errors at specific intervals without continuously interfering with the high-speed signal path, thus enabling both high sampling rates and accurate offset correction.

Inventive Principle:
Principle #19Periodic action

2Speed

If op-amp offset trimming is used for higher speeds, then calibration can be performed, but once calibrated there is no way to adjust for temperature/voltage dependence

Engineering Contradiction:
Improvesampling rateVSAvoidtemperature and voltage adjustment capability
Core Design Contradiction:
SpeedVSAdaptability or versatility

Solution Approach 1:

The patent implements a self-calibrating mechanism where the DAC continuously monitors its own performance parameters and automatically adjusts its operation to compensate for temperature and voltage variations. The system uses built-in reference circuits and feedback loops to detect drift and apply real-time corrections without requiring external intervention, thus maintaining adaptability across varying environmental conditions while operating at high speeds.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent incorporates feedback circuits that continuously monitor the DAC output and compare it against reference values. When temperature or voltage variations cause offset drift, the feedback mechanism detects these changes and automatically adjusts the calibration parameters or switching patterns to compensate, enabling the system to maintain accuracy across different operating conditions without manual re-calibration.

Inventive Principle:
Principle #23Feedback

3Measurement precision

If polysilicon fuses are blown for offset trimming, then offset can be adjusted digitally, but the process is complex and irreversible

Engineering Contradiction:
Improveoffset adjustmentVSAvoidcalibration process complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent replaces the mechanical/physical process of blowing polysilicon fuses with an electronic software-based calibration approach. Instead of permanently altering the circuit through fuse blowing, the system uses programmable logic and digital signal processing to implement offset correction. This substitution transforms an irreversible physical process into a reversible software-based process, reducing complexity and enabling flexible re-calibration.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent implements offset trimming by dynamically changing operational parameters such as switching frequencies, duty cycles, and digital correction codes rather than permanently modifying the circuit structure. These parameter changes allow for flexible offset adjustment through software control, eliminating the need for complex fuse-blown procedures and enabling easy re-calibration if needed.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables accurate calibration across a wide range of speeds and temperatures, reducing op-amp die area and maintaining signal integrity by correcting for offset errors, thus enhancing the DAC's performance in high-speed applications.

Implementation Method 1

a voltage to frequency converter configured to selectively receive the first and second voltage signals and provide first and second output signals at respective first and second frequencies

Methodology Applied
Scientific EffectVoltage to frequency conversion:

Data Source

PatentUS12483255B2Self-calibrating buffered-voltage DAC
Publication Date: 2025.11.25 NXP BV
  • US12483255B2 patent drawing
  • US12483255B2 patent drawing
  • US12483255B2 patent drawing

AI summary

A self-calibrated buffered-voltage DAC includes a DAC configured to receive an input digital signal and output a first analog voltage signal, a buffer amplifier configured to receive the first voltage signal from the DAC and provide a buffered second analog voltage signal, a voltage to frequency converter configured to selectively receive the first and second voltage signals and provide first and second output signals at respective first and second frequencies, a counter configured to receive the output signals from the voltage to frequency converter and provide respective first and second digital output signals corresponding to the respective first and second frequencies, a comparator configured to receive the first and second digital output signals and provide a digital calibration offset, and a DAC error code module configured to receive a digital input code and the digital calibration offset and to provide an offset corrected input digital signal to the DAC.