Buffered Data Transmission Circuit Dynamic Allocation
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Solution Overview
Problem
Existing buffered data transmission circuits require six buffers for two channels, limiting flexibility and efficiency in data transmission.
Innovation Solution
A circuit with four data buffers and tax logic that controls writing and reading access, allowing data to be transmitted from two transmitters to a receiver without restricting the sender, and enabling redundant data channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If six buffers are used for two channels, then data transmission reliability is improved, but device complexity and resource consumption increase
Solution Approach 1:
The patent merges the buffer resources of two channels into a shared pool of four buffers. The control logic dynamically allocates these buffers to different channels based on current transmission needs, allowing one channel to use multiple buffers while another uses fewer, thereby reducing total buffer count while maintaining reliability
Solution Approach 2:
The patent implements dynamic buffer allocation where the control logic can assign different numbers of buffers to different channels based on real-time transmission status. This dynamic adjustment allows the system to maintain high reliability when needed while reducing resource consumption during normal operation
2Duration of action of moving object
If three buffers per channel are used, then continuous data flow is ensured, but loss of substance increases
Solution Approach 1:
The patent implements a pre-allocation mechanism where buffers are reserved in advance for each channel based on predicted transmission needs. The control logic monitors transmission status and proactively allocates buffers before data overflow occurs, ensuring continuous data flow while minimizing the number of buffers actually used at any given time
Solution Approach 2:
The patent makes buffers universal by allowing them to serve multiple channels sequentially. A buffer can be allocated to channel 1, then to channel 2, then back to channel 1, making each buffer perform multiple functions across different channels and time periods, thereby reducing total buffer requirements while maintaining continuous data flow
Data Source
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AI summary
The invention relates to a circuit with a first buffer, a second buffer, a third buffer, a fourth buffer, a first data input for first data, a second data input for second data, a data output, and a control logic. The control logic is designed to connect the first data input to one of the buffers, connect the second data input to one of the buffers, and connect the data output to one of the buffers. The control logic is additionally designed to exchange the buffer currently connected to the first data input with a non-connected buffer if first data is written into the buffer currently connected to the first data input in a valid manner via the first data input, exchange the buffer currently connected to the second data input with the non-connected buffer if second data is written into the buffer currently connected to the second data input in a valid manner via the second data input, and exchange the buffer currently connected to the data output with the non-connected buffer in order to read data if the non-connected buffer has newer data which has been written in a valid manner.