Buffered DIMM Data Bus Training for Faster DRAM Boot Initialization
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Solution Overview
Problem
Existing memory systems require host-controlled training modes for MRE and MRD, leading to increased system boot times due to the need for multiple host writes and reads, which can be inefficient.
Innovation Solution
Perform MRE and MRD training on a buffered DIMM using a receive enable (RCVEN) signal generated by the data buffer, reducing the reliance on host-controlled commands and enabling parallel training across multiple DIMMs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If host-controlled training modes are used for MRE and MRD, then training can be performed with existing control mechanisms, but system boot time increases due to multiple host writes and reads
Solution Approach 1:
The data buffer autonomously generates the RCVEN signal to control MRE and MRD training operations without requiring host intervention. The buffer independently manages its own training sequence by generating receive enable signals that coordinate DRAM reads and data buffer operations, eliminating the need for multiple host writes and reads during training.
Solution Approach 2:
The data buffer pre-generates the RCVEN signal before actual data transfer begins, allowing training operations to be initiated and coordinated without waiting for host commands. This preliminary generation of control signals enables the training sequence to proceed independently and reduces overall training time.
2Productivity
If host-controlled training is used, then training can be performed sequentially, but productivity decreases due to inability to perform parallel training across multiple DIMMs
Solution Approach 1:
Each data buffer independently generates its own RCVEN signal, enabling autonomous training operations on each DIMM without requiring centralized host coordination. This self-service capability allows multiple DIMMs to undergo training simultaneously in parallel, significantly improving training throughput while maintaining operational simplicity.
3Loss of time
If multiple host writes and reads are performed for training, then training can be completed with existing protocols, but the number of operations increases leading to longer boot time
Solution Approach 1:
The training control operations are extracted from the host and transferred to the data buffer itself. The buffer generates the RCVEN signal and manages the training sequence independently, removing the need for multiple host writes and reads. This extraction of control functions reduces the number of host operations required during training.
Solution Approach 2:
The RCVEN signal acts as an intermediary control mechanism that the data buffer generates to coordinate training operations. This intermediate signal enables the buffer to autonomously manage the training sequence between DRAM and buffer without requiring direct host intervention for each operation, reducing the total number of host commands needed.
Data Source
AI summary
System boot time is decreased by performing Memory Receive enable (MRE) training and MDQ-MDQS Read Delay (MRD) training on a buffered Dual In-Line Memory Module (DIMM). MRE training configures the time at which a data buffer on the buffered DIMM enables its receivers to capture data read from DRAM integrated circuits on a MDQ/MDQS bus between the DRAM and the data buffer on the DIMM. After the MRE training has completed, the data buffer is configured to enable the data buffer receivers to receive data on the MDQ bus on the buffered DIMM during the preamble of the incoming MDQS burst from a read transaction in the DRAM. MRD training tunes the relationship between the MDQ/MDQS bus to ensure sufficient setup and hold eye margins for MDQ so that the data buffer optimally samples the data driven by the DRAM during reads of the DRAM.