Buffered Flipped Voltage Follower LDO With Feed-Forward Compensation
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Solution Overview
Problem
Digital-like circuit architectures suffer from reduced power supply rejection compared to their purely analog predecessors, leading to instability and insufficient performance in high-frequency applications like RF CDACs, especially with emerging 5G communication standards.
Innovation Solution
A feed-forward frequency compensation structure is introduced for buffered flipped voltage follower-based low dropout regulators, enabling ultra-high regulation bandwidths and low output impedances while maintaining stability and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If digital-like circuit architectures are used, then power consumption is reduced and silicon area is minimized, but power supply rejection is heavily reduced or vanished
Solution Approach 1:
The circuit is divided into digital-like switching elements and analog compensation components. The digital-like portion handles basic logic functions with low power consumption, while the analog feed-forward compensation section specifically addresses power supply rejection, allowing each segment to optimize its own performance characteristics.
Solution Approach 2:
A feed-forward compensation circuit is introduced as an intermediary mechanism between the digital-like circuit and the power supply. This compensation circuit actively counteracts power supply variations before they affect the digital circuit operation, thereby restoring power supply rejection without requiring the entire circuit to be analog.
2Productivity
If digital-like circuit architectures are used, then technology scaling benefits are maximized, but analog properties become heavily dependent on supply voltage variations
Solution Approach 1:
The feed-forward compensation circuit performs preliminary action by anticipating and counteracting the effects of supply voltage variations before they can degrade the analog properties. This allows the digital-like circuit to maintain stable analog behavior (delay, rise/fall times) even as supply voltage fluctuates during operation.
Solution Approach 2:
The compensation circuit dynamically adjusts its operation based on detected supply voltage variations, changing its parameters to counteract the specific variations occurring. This allows the system to maintain stable analog properties across different supply conditions while preserving the scalability benefits of digital-like architecture.
3Speed
If feed-forward frequency compensation is added, then regulation bandwidth is increased and output impedance is reduced, but circuit complexity increases
Solution Approach 1:
The feed-forward compensation is applied locally at critical nodes within the circuit rather than throughout the entire system. By targeting specific locations where supply rejection is most needed, the patent achieves high regulation bandwidth and low output impedance with minimal additional circuitry, avoiding unnecessary complexity in regions where compensation is not required.
Data Source
AI summary
Examples relate to a buffered flipped voltage follower circuit arrangement, low dropout voltage regulators, a capacitive digital-to-analog converter, a transceiver for wireless communication, a mobile communication device, a base station transceiver, and to a method for forming a buffered flipped voltage follower circuit arrangement. The buffered flipped voltage follower circuit arrangement comprises a first transistor (MP) comprising a first terminal, a second terminal, and a gate terminal. The buffered flipped voltage follower circuit arrangement comprises a second transistor (MC) comprising a first terminal, a second terminal and a gate terminal. The buffered flipped voltage follower circuit arrangement comprises a buffer circuit comprising an input terminal and an output terminal. The buffered flipped voltage follower circuit arrangement a feed-forward compensation circuit (−gmf) comprising an input terminal and an output terminal. The first terminal of the first transistor (MP) is coupled to a supply voltage of the flipped voltage follower circuit. The second terminal of the first transistor (MP) is coupled with the first terminal of the second transistor (MC) and with an output voltage terminal of the buffered flipped voltage follower circuit arrangement. The second terminal of the second transistor (MC) is coupled with the input terminal of the buffer circuit and with the output terminal of the feed-forward compensation circuit (−gmf). The gate terminal of the first transistor (MP) is coupled with the output terminal of the buffer circuit and with the input terminal of the feed-forward compensation circuit (−gmf).