Buffered Interconnect Routing via Macro Layer Buffer Placement
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Solution Overview
Problem
Conventional IC routing tools are constrained by cell placement, forcing buffered interconnects to take circuitous routes, leading to increased power consumption and signal delays due to the need for buffers in circuit layers and the restriction to taxicab geometry.
Innovation Solution
A novel routing technique that defines a boundary based on buffer driving length, trims blockages, and iteratively selects line segments to place buffers, allowing for more direct routing of interconnects while considering the areas required by buffers, thereby reducing interconnect length and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If buffered interconnects are routed in circuit layers following conventional IC routing tools, then cell placement constraints are satisfied, but interconnect length increases and power consumption increases
Solution Approach 1:
The patent moves buffer placement from the circuit layer to the macro layer, changing the dimensional constraint environment. This allows buffers to be positioned in regions not occupied by standard circuit cells, enabling more direct routing paths that reduce interconnect length and power consumption while still satisfying placement constraints.
Solution Approach 2:
The patent introduces a boundary-based intermediary structure that mediates between cell placement constraints and buffer placement freedom. The boundary defines a candidate area that respects cell locations while providing flexibility for buffer positioning, thus resolving the contradiction between manufacturing constraints and energy efficiency.
2Ease of manufacture
If buffered interconnects are routed in circuit layers following conventional IC routing tools, then cell placement constraints are satisfied, but interconnect length increases
Solution Approach 1:
By relocating buffer placement to the macro layer, the patent enables routing paths that are not constrained by the rigid grid and cell boundaries of the circuit layer. This dimensional shift allows for shorter, more direct interconnect paths while maintaining compliance with placement constraints.
Solution Approach 2:
The patent segments the routing problem into two independent parts: cell placement in the circuit layer and buffer placement in the macro layer. This segmentation allows each sub-problem to be optimized independently, resulting in shorter interconnect lengths without compromising placement validity.
3Loss of time
If buffers are placed to minimize paths to clock ports, then signal delays are reduced, but device complexity increases
Solution Approach 1:
The boundary-based candidate area definition enables a self-service mechanism where the routing algorithm automatically identifies valid buffer locations without complex constraint checking. The boundary itself encodes the placement constraints, allowing the system to reduce signal delays through intuitive buffer placement while keeping the algorithm relatively simple.
Data Source
AI summary
A system and method for routing a buffered interconnect in an IC from a source cell to a target cell thereof. In one embodiment, the system includes: (1) a path tracer operable to designate the source cell as a current node and construct a path toward the target node by: (1a) defining a boundary about the current node based on a buffer driving length, (1b) trimming the boundary by any blockage therein to yield a candidate area for placing a buffer, (1c) dividing the boundary into line segments, (1d) selecting a closest, valid one of the line segments to the target cell as the current node and (1e) repeating the defining, trimming, dividing and selecting the closest, valid one until the current node lies within the buffer driving length and (2) a buffer placer associated with the path tracer and operable to select a location along the path to place the buffer.