Buffered Memory Modules With Wide/Narrow Data Modes
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Solution Overview
Problem
The number of memory modules that can be connected to a single channel in memory systems is limited, leading to degraded signaling integrity and reduced signal rates due to increased load on the channel.
Innovation Solution
A memory module design that supports both wide and narrow data modes, utilizing data and address buffers to reduce loading on the connector, allowing point-to-point connections with DRAM components, and enabling flexible data width configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more memory modules are connected to a single channel, then memory capacity increases, but signaling integrity degrades and signal rates are reduced
Solution Approach 1:
The patent divides a single wide data bus into multiple narrower data sub-buses, with each sub-bus connecting to a separate memory module. This segmentation reduces the loading on each individual connection, allowing more modules to be connected while maintaining signaling integrity. The memory controller is also segmented to handle multiple sub-buses independently.
Solution Approach 2:
The patent transitions from a single-dimension wide bus architecture to a multi-dimensional architecture where multiple narrow sub-buses operate in parallel. This dimensional change allows the system to connect more memory modules by distributing the load across multiple independent communication paths rather than overloading a single channel.
2Quantity of substance
If more memory modules are connected to a single channel, then memory capacity increases, but signal rates are reduced
Solution Approach 1:
The data bus is segmented into multiple independent sub-buses, each operating at high signal rates with dedicated connections to specific memory modules. This segmentation prevents signal rate degradation by avoiding the loading effects that occur when multiple modules share a single wide bus.
Solution Approach 2:
The architecture moves from a single shared communication channel to multiple parallel communication dimensions. Each sub-bus operates independently in its own dimension, maintaining high signal rates while collectively providing increased memory capacity through parallel data paths.
3Productivity
If data width is increased, then data transfer capacity improves, but loading on the connector increases
Solution Approach 1:
The wide data bus is segmented into multiple narrower sub-buses, each connecting to specific memory modules. This segmentation maintains high data transfer capacity through parallel sub-buses while reducing the loading on each individual connector, as each sub-bus carries only a portion of the total data width.
Solution Approach 2:
The system achieves high data transfer capacity not by increasing the width of a single bus, but by adding multiple parallel bus dimensions. Each sub-bus operates at a manageable width with reduced connector loading, while the aggregate bandwidth across all sub-buses provides the high data transfer capacity needed.
Data Source
AI summary
Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.