Buffered Neural Network Hardware for Die Size Reduction
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Solution Overview
Problem
Conventional digital hardware implementations of neural networks with convolutional layers and small kernels fail to reduce die size or the number of neurons, despite reusing weight values for multiple calculations.
Innovation Solution
The method involves transforming a trained convolutional neural network into a buffered neural network by splitting it into a left subnetwork and a right subnetwork, interconnected via a buffer, which reduces the number of neurons and die size by reusing computing elements for convolution, pooling, and other computations, and selecting layers based on a measure of locality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional digital hardware implementations reuse weight values in multiple calculations, then memory size is reduced, but die size is not reduced
Solution Approach 1:
The patent merges multiple identical computing elements into a single shared computing element that serves multiple neurons. By combining several neurons with identical structures into one reusable computing element that can be dynamically configured, the hardware reduces die size while maintaining computational functionality. This merging approach allows the same physical hardware to perform calculations for multiple neurons sequentially, rather than requiring separate dedicated hardware for each neuron.
Solution Approach 2:
The patent creates universal computing elements that can perform multiple functions by being dynamically reconfigured. A single computing element can serve multiple neurons by changing its configuration based on which neuron needs computation at any given time. This multi-functionality allows the hardware to reduce the total number of physical computing elements needed, thereby reducing die size while maintaining the ability to support all neurons in the network.
2Area of stationary object
If the number of neurons is reduced using buffers, then die size is reduced, but computational complexity increases
Solution Approach 1:
The patent uses buffers to store intermediate computation results before they are needed by subsequent layers. By pre-computing and storing results in buffers, the system avoids redundant calculations when the same data needs to be processed multiple times. This preliminary action reduces the overall computational complexity because computations are performed once and stored, rather than being repeated for each neuron or computation pass.
Solution Approach 2:
The patent introduces buffers as intermediary storage between computational layers. These buffers act as mediators that hold intermediate results, allowing the system to decouple computation from consumption. The buffers enable efficient data sharing between different computational operations without requiring repeated computations, thereby reducing computational complexity while enabling fewer neurons to be implemented in hardware.
3Area of stationary object
If buffers are inserted to reduce neurons, then die size is reduced, but memory requirements increase
Solution Approach 1:
The patent applies buffering selectively to specific layers and neurons based on their local characteristics and computational patterns. Rather than uniformly buffering all neuron outputs, the system identifies which layers and neurons benefit most from buffering and applies it locally. This selective approach ensures that memory is allocated only where it provides the greatest benefit in reducing die size, optimizing the trade-off between memory usage and hardware footprint.
Solution Approach 2:
The patent implements buffering for only a subset of neurons and layers rather than all neurons throughout the network. By applying buffering partially to the most beneficial locations, the system achieves significant die size reduction without the full memory overhead of universal buffering. This partial action approach optimizes the balance between memory requirements and die size reduction by focusing resources where they provide maximum benefit.
Data Source
AI summary
A hardware apparatus implements a neural network. In some embodiments, the neural network is a trained convolutional neural network. The hardware apparatus includes a network of interconnected neurons (e.g., implemented in operational amplifiers and resistors). The network of interconnected neurons has a plurality of subnetworks, including a left subnetwork and a right subnetwork. The left and right subnetworks are interconnected via a buffer. The left subnetwork of neurons and the right subnetwork of neurons are configured to operate at different frequencies and/or the right subnetwork is configured to operate conditionally based on content of the buffer.