Buffered Ring Oscillator Delay Circuit for Low-Jitter Clocks
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Solution Overview
Problem
Conventional ring oscillators experience significant current leakage and signal jitter due to increased stages or transistor dimensions, leading to high power consumption and poor signal quality.
Innovation Solution
A ring oscillator design featuring inverting delay units with buffers and delay circuits that select reference voltages based on input signal voltage levels, reducing power consumption by minimizing unnecessary transistor activation and preventing short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the number of stages of inverters is increased or transistor dimensions are enlarged to reduce clock signal frequency, then the frequency control is achieved, but current leakage increases significantly and power consumption increases
Solution Approach 1:
The inverter stage is segmented into separate components: a buffer unit and a delay unit. The buffer unit handles signal level restoration while the delay unit provides time delay, with transistors controlled by control signals. This segmentation allows independent optimization of each unit, reducing simultaneous transistor conduction and current leakage while maintaining frequency control capability.
Solution Approach 2:
The delay unit employs dynamically controllable transistors whose on/off states are controlled by control signals. This dynamic control allows the delay time to be adjusted without changing the number of stages or transistor dimensions, enabling frequency control without the current leakage penalty of conventional static designs.
2Speed
If the number of stages of inverters is increased to reduce clock signal frequency, then frequency control is achieved, but the circuit complexity increases
Solution Approach 1:
The invention changes the control parameter from structural (number of stages) to parametric (delay time of each unit). By adjusting the delay time parameter of each inverting delay unit through control signals, frequency control is achieved without increasing the number of stages, thus reducing circuit complexity while maintaining frequency adjustment capability.
3Speed
If transistor dimensions are enlarged to reduce clock signal frequency, then frequency control is achieved, but current leakage increases significantly
Solution Approach 1:
The inverter is segmented into buffer and delay units with separate transistor groups. The buffer unit transistors and delay unit transistors are controlled independently by control signals, preventing simultaneous conduction. This segmentation reduces current leakage without requiring smaller transistor dimensions, enabling frequency control with reduced power consumption.
4Speed
If conventional inverters are used with increased stages, then frequency control is achieved, but signal jitter increases greatly
Solution Approach 1:
The inverter stage is segmented into buffer and delay units. The buffer unit restores signal levels to reduce jitter accumulation, while the delay unit provides controlled time delay. This segmentation prevents the jitter accumulation problem of conventional multi-stage inverters, maintaining signal quality while enabling frequency control.
Data Source
AI summary
A ring oscillator includes a plurality of inverting delay units serially connected in a form of a ring. Each of the inverting delay units receives an input signal and generates an output signal, and each of the inverting delay units includes a buffer and a delay circuit. The buffer has an input terminal and an output terminal. The input terminal receives the input signal, and the output terminal generates a buffered input signal. The delay circuit serves to provide a first time delay and a second time delay. Besides, according to a voltage level of the buffered input signal, the delay circuit provides a first reference voltage to generate the output signal after the first time delay or provides a second reference voltage to generate the output signal after the second time delay.