Buffered Flipped Voltage Follower With Feed-Forward Compensation
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Solution Overview
Problem
Digital-like circuit architectures, such as those used in RF CDACs, suffer from reduced power supply rejection and limited regulation bandwidth, making them inadequate for high-frequency applications like 5G communication standards, which can be exacerbated by the introduction of large external capacitors that increase cost and complexity.
Innovation Solution
A buffered flipped voltage follower circuit with a feed-forward frequency compensation scheme is introduced, providing ultra-high regulation bandwidth and low output impedance, stabilizing the circuit and improving efficiency without significant power consumption increases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If digital-like circuit architectures are used, then power consumption is reduced and silicon area is minimized, but power supply rejection is heavily reduced and analog properties become dependent on supply voltage variations
Solution Approach 1:
The circuit is divided into two separate loops: an inner high-frequency loop for fast transient response and an outer low-frequency loop for accurate DC regulation and high power supply rejection. This segmentation allows each loop to be optimized for its specific function while working together to resolve the contradiction between low power consumption and high reliability.
Solution Approach 2:
A buffer stage is introduced as an intermediary between the digital-like core circuit and the analog output stage. This buffer provides high input impedance to minimize loading effects on the digital circuit (maintaining low power consumption) while providing low output impedance for strong analog drive capability and improved power supply rejection.
2Speed
If regulation bandwidth is increased to meet high-frequency applications, then performance for 5G communication is improved, but circuit complexity and power consumption increase
Solution Approach 1:
The regulation function is segmented into two frequency domains: the inner loop handles high-frequency transient regulation with bandwidth sufficient for 5G applications, while the outer loop handles low-frequency DC regulation and power supply rejection. This frequency-domain segmentation achieves wide effective bandwidth without requiring a single complex high-bandwidth control loop.
Solution Approach 2:
The circuit employs dynamic biasing where the common-gate amplifier's bias current is adjusted based on operating conditions. This allows the inner loop bandwidth to be dynamically optimized for high-frequency performance when needed, while consuming minimal power during steady-state operation, thus achieving high speed without proportionally increasing complexity and power consumption.
3Reliability
If large external capacitors are introduced to stabilize the circuit, then power supply rejection is improved, but cost and device complexity increase
Solution Approach 1:
The buffer stage acts as an intermediary impedance transformation stage that provides low output impedance without requiring large external capacitors. By actively driving the output with high current capability through the common-gate amplifier and buffer, the circuit achieves strong power supply rejection and transient response using only on-chip compensation capacitance, eliminating the need for large external capacitors.
Solution Approach 2:
The circuit changes the impedance parameters dynamically through the buffer stage and feed-forward path. Instead of using large capacitors to lower output impedance at all frequencies, the active buffer provides low output impedance through high current drive capability, while the feed-forward path adjusts the effective impedance across different frequency ranges, achieving stability without large external components.
Data Source
AI summary
Examples relate to a buffered flipped voltage follower circuit arrangement, low dropout voltage regulators, a capacitive digital-to-analog converter, a transceiver for wireless communication, a mobile communication device, a base station transceiver, and to a method for forming a buffered flipped voltage follower circuit arrangement. The buffered flipped voltage follower circuit arrangement comprises a first transistor (Mp) comprising a first terminal, a second terminal and a gate terminal. The buffered flipped voltage follower circuit arrangement comprises a second transistor (Mc) comprising a first terminal, a second terminal and a gate terminal. The buffered flipped voltage follower circuit arrangement comprises a buffer circuit comprising an input terminal and an output terminal. The buffered flipped voltage follower circuit arrangement a feed-forward compensation circuit (−gmf) comprising an input terminal and an output terminal. The first terminal of the first transistor (Mp) is coupled to a supply voltage of the flipped voltage follower circuit. The second terminal of the first transistor (Mp) is coupled with the first terminal of the second transistor (Mc) and with an output voltage terminal of the buffered flipped voltage follower circuit arrangement. The second terminal of the second transistor (Mc) is coupled with the input terminal of the buffer circuit and with the output terminal of the feed-forward compensation circuit (−gmf). The gate terminal of the first transistor (MP) is coupled with the output terminal of the buffer circuit and with the input terminal of the feed-forward compensation circuit (−gmf).