Buffered Write Circuitry for Memory Command Scheduling
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Solution Overview
Problem
Managing complex sequences of memory access commands in multi-group memory systems is complicated due to timing specifications, leading to potential collisions and underutilization of command and data buses, even with the concept of additive latency.
Innovation Solution
The implementation of buffered write circuitry that reorders write operations to allow later received read commands to be executed before completing earlier write operations, using a write command buffer and column address buffer to manage write commands, addresses, and data, thereby reducing timing gaps and improving scheduling efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If write commands are issued to memory devices according to timing specifications, then proper operation of memory devices is ensured, but timing gaps between commands occur resulting in underutilization of command and data buses
Solution Approach 1:
The patent introduces additive latency (AL) which allows write commands to be issued earlier than traditionally required, holding them in a buffer until the appropriate time for execution. This preliminary action enables better utilization of the command bus by keeping it busy with command issuance while the memory device internally manages the timing of actual write operations, thereby improving bus utilization without compromising reliable operation.
2Productivity
If additive latency is used to improve command bus efficiency, then sustainable bandwidths are achieved, but timing gaps between commands still result in underutilization of data buses
Solution Approach 1:
The patent buffers write data along with write commands, allowing data to be prepared and held in advance. This enables the data bus to be utilized more effectively by reducing idle time between data transfer operations, as data is ready to be transferred as soon as the memory device is prepared to receive it, rather than waiting for the complete write cycle to finish.
Solution Approach 2:
The patent introduces a write data buffer as an intermediary between the data bus and the memory device. This buffer decouples the data transfer timing from the write command timing, allowing the data bus to operate continuously by holding data ready for transfer, while the memory device processes writes at its own pace. This intermediary structure eliminates data bus idle time without requiring the memory device to operate faster.
3Reliability
If complex sequences of memory access commands are managed in multi-group memory systems, then timing specifications are met, but command scheduling becomes very complicated
Solution Approach 1:
The patent applies additive latency to write commands in multi-group memory systems, allowing write commands to be issued in advance and held in buffers. This preliminary action simplifies the controller's scheduling task by decoupling command issuance from command execution timing, enabling the controller to issue commands to multiple memory groups in a simplified sequence while the memory devices and their internal buffers manage the complex timing requirements.
Data Source
AI summary
Memories, buffered write command circuits, and methods for executing memory commands in a memory. In some embodiments, read commands that are received after write commands are executed internally prior to executing the earlier received write commands. Write commands are buffered so that the commands can be executed upon completion of the later received read command. One example of a buffered write command circuit includes a write command buffer to buffer write commands and propagate buffered write commands therethrough in response to a clock signal and further includes write command buffer logic. The write command buffer logic generates an active clock signal to propagate the buffered write commands through the write command buffer for execution, suspends the active clock signal in response to receiving a read command after the write command is received, and restarts the active clock upon completion of the later received read command.