Buffering Candidate Pruning for IC Timing Evaluation

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Solution Overview

Problem

Conventional buffering techniques in electronic design automation (EDA) systems for integrated circuit (IC) design result in slow run-time due to the need for substantial processing resources to evaluate numerous buffering candidates, which can be computationally intensive and time-consuming.

Innovation Solution

Implementing a cost-based pruning method that uses a first timing model for quick estimates and a second timing model for accurate evaluations, allowing for the pruning of buffering candidates based on cost, timing improvement, or a combination of both, to reduce the number of candidates evaluated, thereby improving processing efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional buffering techniques evaluate numerous buffering candidates using accurate timing models, then the reliability of buffering solution selection is improved, but the run-time and computational resources required increase significantly

Engineering Contradiction:
Improvebuffering solution selection accuracyVSAvoidbuffering process run-time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The evaluation process is segmented into two phases: a quick evaluation phase using a first timing model that provides approximate timing values, and a detailed evaluation phase using a second timing model. This segmentation allows the system to quickly filter out poor candidates before applying computationally intensive accurate evaluation, thereby reducing overall run-time while maintaining solution reliability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs preliminary evaluation of buffering candidates using a fast timing model before conducting detailed accurate evaluation. This preliminary action identifies and eliminates unpromising candidates early in the process, preventing wasteful consumption of computational resources on candidates that would not yield optimal results even with accurate evaluation.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If comprehensive timing analysis is performed on all buffering candidates, then the manufacturing precision of timing characteristics is improved, but the processing resources and complexity increase

Engineering Contradiction:
Improvetiming characteristic accuracyVSAvoidevaluation process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The evaluation approach dynamically adapts the level of analysis applied to each candidate based on preliminary assessment. Candidates that pass initial screening undergo comprehensive timing analysis, while others receive minimal evaluation. This dynamic adjustment optimizes the balance between timing characteristic accuracy and processing complexity.

Inventive Principle:
Principle #15Dynamics

3Productivity

If all buffering candidates are evaluated using the second timing model, then the productivity of selecting optimal buffering solutions is improved, but the computational resources required become excessive

Engineering Contradiction:
Improvebuffering solution selection efficiencyVSAvoidcomputational resource consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The system extracts and evaluates only the most promising buffering candidates using the computationally intensive second timing model, rather than evaluating all candidates. By taking out only the relevant subset of candidates for detailed analysis, the system maintains high productivity in selecting optimal solutions while dramatically reducing computational resource consumption.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS11520959B1Pruning of buffering candidates for improved efficiency of evaluation
Publication Date: 2022.12.06 CADENCE DESIGN SYST INC
  • US11520959B1 patent drawing
  • US11520959B1 patent drawing
  • US11520959B1 patent drawing

AI summary

An integrated circuit (IC) design is accessed from a database in memory. The IC design comprises a route connecting a source to a sink. A set of buffering candidates for buffering are generated for the net. A timing improvement associated with a buffering candidate in the set of buffering candidates is determined using a first timing model. The buffering candidate is pruned from the set of buffering candidates based on the timing improvement and a cost associated with the buffering candidate. The pruned set of buffering candidates is evaluated using a second timing model, and a buffering solution for the net is selected from the pruned set of buffering candidates based on a result of the evaluating. The IC design is updated to include the buffering solution selected for the net.