Bufferless Hoplite Router for FPGA NOC Resource Efficiency
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Solution Overview
Problem
Current FPGA network-on-chip (NOC) designs are inefficient in terms of resource usage and bandwidth, with complex systems consuming many resources while delivering limited bandwidth, and lack practical solutions for high-bandwidth interconnection of client cores and high-speed interfaces.
Innovation Solution
The Hoplite router and NOC system implement a directional torus deflection router with a bufferless design, using optimized technology mapping and modular routing functions to achieve efficient interconnection of client cores with minimal resource consumption, supporting wide high-bandwidth links and concurrent multicast message delivery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If complex buffered Virtual Channel routers are used to provide high-bandwidth interconnection, then bandwidth capacity is improved, but device complexity and resource consumption increase significantly
Solution Approach 1:
The patent extracts and removes the buffer component from traditional buffered Virtual Channel routers, creating a bufferless router architecture. This extraction eliminates the complexity and resource consumption associated with buffer management while maintaining high-bandwidth capability through direct throughput routing between client cores and memory interfaces.
Solution Approach 2:
Instead of following the conventional approach of using buffers to manage data flow and handle congestion, the patent inverts the approach by designing a bufferless architecture that relies on deflection routing and dimension-order routing algorithms to manage data flow without storage elements, thereby reducing complexity while maintaining bandwidth.
2Productivity
If traditional buffered router designs are implemented, then message delivery capability is improved, but resource consumption and area usage increase
Solution Approach 1:
The patent removes buffers from the router architecture, eliminating the significant area consumption associated with buffer storage elements. The bufferless design maintains message delivery capability through deflection routing that redirects messages around congested areas without requiring local storage.
Solution Approach 2:
The bufferless router employs self-service mechanisms where the routing algorithm dynamically adapts to network conditions and redirects messages in real-time without requiring buffer storage. The dimension-order routing algorithm automatically manages message flow by routing along predetermined dimensional paths, eliminating the need for buffer-based flow control.
3Productivity
If buffered Virtual Channel routers with multiple virtual channels are used, then concurrency and throughput are improved, but device complexity and resource usage increase
Solution Approach 1:
The patent extracts and removes the Virtual Channel mechanism from the router design, eliminating the complexity associated with multiple virtual channels, virtual channel arbitration, and flow control protocols. Throughput is maintained through the bufferless deflection routing architecture that handles concurrency without virtual channel abstraction.
4Adaptability or versatility
If conventional NOC designs with buffers and virtual channels are implemented, then message routing flexibility is improved, but power consumption and resource usage increase
Solution Approach 1:
The patent removes buffers and virtual channel mechanisms that consume significant power, creating a low-power bufferless router. Routing flexibility is maintained through deflection routing algorithms that can dynamically redirect messages around congested areas and through dimension-order routing that provides adaptable path selection without requiring buffer-based flow control.
Data Source
AI summary
A configurable directional 2D router for Networks on Chips (NOCs) is disclosed. The router, which may be bufferless, is designed for implementation in programmable logic in FPGAs, and achieves theoretical lower bounds on FPGA resource consumption for various applications. The router employs an FPGA router switch design that consumes only one 6-LUT or 8-input ALM logic cell per router per bit of router link width. A NOC comprising a plurality of routers may be configured as a directional 2D torus, or in diverse ways, network sizes and topologies, data widths, routing functions, performance-energy tradeoffs, and other options. The router and NOC enable feasible FPGA implementation of large integrated systems on chips, interconnecting hundreds of client cores over high bandwidth links, including compute and accelerator cores, industry standard IP cores, DRAM/HBM/HMC channels, PCI Express channels, and 10G/25G/40G/100G/400G networks.