Multi-Level Cell Programming Without Buffer Using Balanced Gray Code
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Solution Overview
Problem
Existing methods for programming multi-level flash memory cells, such as foggy-fine programming, require additional hardware resources like single-level cells for buffering, increasing complexity and cost while reducing available space for user data and overprovisioning due to the need for precise voltage control and error correction.
Innovation Solution
An optimized multiphase mapping with a balanced Gray code is used to transition from a first programming phase to a second phase, minimizing average voltage change and eliminating the need for a buffer, allowing direct read and write operations without additional caching, thus simplifying device design and improving performance metrics like write endurance and read/write bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If foggy-fine programming approach is used for precise programming of multi-level cells, then programming precision is improved, but device complexity increases due to additional hardware resources required
Solution Approach 1:
The patent merges the foggy phase and fine phase programming operations into a unified multiphase programming process that uses the same memory cell array for both phases. The mapping mechanism combines multiple programming phases while using balanced Gray codes to transition between phases, eliminating the need for separate buffer memory and reducing overall device complexity while maintaining programming precision.
Solution Approach 2:
The memory cell array is designed to serve multiple functions: it acts as both the programming target and the storage medium for intermediate states during multiphase programming. The same physical resources are used across different programming phases, making the system more versatile and reducing the need for dedicated hardware components for each phase.
2Manufacturing precision
If single-level cells are used for buffering in foggy-fine programming, then programming precision is improved, but available space for user data decreases
Solution Approach 1:
The patent eliminates the need for separate buffer memory by merging the programming operations so that intermediate foggy phase results are stored directly in the target memory cell array. This integration removes the space requirement for dedicated buffer cells, increasing the area available for user data while maintaining programming precision through the multiphase approach.
3Manufacturing precision
If additional hardware resources are allocated for error correction, then programming precision is improved, but cost increases
Solution Approach 1:
The balanced Gray code mapping mechanism provides inherent error correction capabilities through its mathematical properties. The structured transition between programming phases using balanced Gray codes naturally minimizes errors without requiring additional expensive error correction hardware, making the system self-sufficient in maintaining precision while controlling costs.
4Productivity
If multiphase mapping with balanced Gray code is used, then programming time is reduced, but mapping complexity increases
Solution Approach 1:
The patent uses balanced Gray codes to systematically change the mapping parameters between programming phases. This mathematical approach provides a structured method for transitioning between phases that reduces the number of programming steps required, thereby reducing programming time while keeping the mapping complexity manageable through the use of well-defined Gray code sequences.
Data Source
AI summary
Disclosed are systems and methods for providing programming of multi-level memory cells using an optimized multiphase mapping with a balanced Gray code. A method includes programming, in a first phase, a first portion of data into memory cells in a first-level cell mode. The method may also include reading, from the memory cells, the programmed first portion of the data. The method may also include programming, in a second phase, a second portion of the data into the memory cells in a second-level cell mode, wherein programming the second phase is based on applying, to the read first portion of the data, a mapping from the first-level cell mode to the second-level cell mode. The mapping may be selected based on minimizing an average voltage change of the memory cells from the first to second phase while maintaining a balanced Gray code.