Bufferless Nonblocking Network on Chip Architecture
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Solution Overview
Problem
Conventional network-on-chip (NoC) designs face challenges in meeting bandwidth demands and latency requirements in a power-efficient manner due to the use of buffered approaches, which lead to deadlocks, congestion, and high power consumption, silicon area usage, and complexity.
Innovation Solution
A bufferless nonblocking NoC design that eliminates buffers and uses a crossbar switch with discrete channels for communication links, allowing for predetermined communication pathways and efficient data transmission without sophisticated congestion control or routing arbitration schemes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If buffers are used in NoC design, then packets can be stored and routing flexibility is improved, but power consumption increases and deadlocks may occur
Solution Approach 1:
The patent removes buffers from the NoC architecture entirely, extracting the problematic component that causes both power consumption and deadlock issues. The solution uses a bufferless approach where packets are transmitted directly without storage, eliminating the energy consumption associated with buffer operation while maintaining routing flexibility through sophisticated routing algorithms.
2Quantity of substance
If buffers are used in NoC design, then packets can be stored, but silicon area increases
Solution Approach 1:
By extracting and removing buffers from the NoC architecture, the patent eliminates the silicon area required for buffer implementation. The bufferless design transmits packets directly through routing nodes without requiring storage space, significantly reducing the overall silicon area occupied by the NoC while maintaining packet transmission capability.
3Reliability
If sophisticated routing algorithms are used to prevent deadlocks, then deadlock-free operation is achieved, but device complexity increases
Solution Approach 1:
Instead of using complex routing algorithms to prevent deadlocks in buffered networks, the patent inverts the approach by eliminating buffers entirely. This inversion simplifies the system because the deadlock prevention mechanism becomes trivial - without buffers, there is nothing to cause deadlocks. The routing algorithm complexity is reduced to basic forwarding logic while maintaining reliability.
4Quantity of substance
If buffered approach is used, then packets can be stored and routed, but congestion control becomes more complex
Solution Approach 1:
By removing buffers from the NoC architecture, the patent eliminates the need for complex congestion control mechanisms. Without buffers, congestion is handled through simple packet dropping or routing decisions at the network layer, significantly reducing the complexity of congestion control while maintaining packet transmission functionality.
Data Source
AI summary
Network on Chips (NoC)s with a bufferless and nonblocking architecture are described. Core processors are communicatively coupled together on a substrate with a set of routing nodes based on nonblocking process. A network component routes data packets through the routing nodes and the core processors via communication links. A bufferless cross bar switch facilitates the communication of the data packets and/or path setup packets through the communication links among source processors and destination processors. The communication links include one or more channels, in which a channel comprises a data sub-channel, an acknowledgement sub-channel and a release sub-channel.