Software Build DAG Transformation for Parallel Task Scheduling

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Solution Overview

Problem

Existing build systems limit parallelism due to dependencies that require all tasks in a target to be completed before starting, leading to inefficient use of processing units.

Innovation Solution

A method and apparatus that transforms a directed acyclic graph (DAG) by identifying independent executable tasks and scheduling them across multiple processing units, using gates like 'begin compiling' and 'module ready' to allow tasks to run concurrently.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the build system waits for every task in target B to finish before any tasks for target A can begin, then the build model remains simple and reliable, but parallelism opportunities are limited and build time increases

Engineering Contradiction:
Improvebuild model reliabilityVSAvoidbuild throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent segments the build process into fine-grained tasks and introduces intermediate gates (begin compiling gate, modules ready gate) that divide the dependency chain. This allows target A's compilation tasks to begin once headers are copied, rather than waiting for the entire target B to complete, thereby enabling parallel execution while maintaining build correctness

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary actions by identifying and executing tasks that can be done in advance, such as copying headers and creating directory structures before compilation begins. This allows compilation tasks to start earlier without compromising the integrity of the build process

Inventive Principle:
Principle #10Preliminary action

2Ease of operation

If the build system uses traditional dependency waiting, then task execution order is simple to manage, but processing units are underutilized and build time is prolonged

Engineering Contradiction:
Improvetask scheduling simplicityVSAvoidbuild time
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The patent dynamically adjusts the build schedule by introducing intermediate gates that allow flexible task execution. The system transitions from a static, fully-sequential model to a dynamic model where tasks can begin as soon as their specific prerequisites are met, optimizing resource utilization while maintaining correctness

Inventive Principle:
Principle #15Dynamics

3Productivity

If the build system transforms dependencies to allow parallel execution, then build time is reduced and processing units are utilized efficiently, but the build model complexity increases

Engineering Contradiction:
Improvebuild throughputVSAvoidbuild model complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces intermediary gates (begin compiling gate, modules ready gate) that mediate between dependency targets and compilation tasks. These gates act as intermediaries that track specific completion conditions, allowing parallel execution while managing complexity through structured intermediate control points

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12619409B2Systems and methods for eager software build
Publication Date: 2026.05.05 APPLE INC
  • US12619409B2 patent drawing
  • US12619409B2 patent drawing
  • US12619409B2 patent drawing

AI summary

A method and apparatus of a device that builds a target using a plurality of processing units is described. In an exemplary embodiment, the device receives a build file for the target, where the build file identifies a plurality of dependencies and the first target is depended on a second target. In addition, the device generates a directed acyclic graph for the first target from the plurality of dependencies. Furthermore, the device transforms the directed acyclic graph by transforming the first set of dependencies to a second set of dependencies and the second set of dependency includes the first dependency that is from a first node in the first target to a second node of a second target. The device additionally identifies a plurality of independent executable tasks, where each of the plurality of independent executable tasks is executable without an unresolved dependency and at least one of the plurality of executable tasks is associated with the second set of dependencies of the transformed directed acyclic graph. The device further schedules the plurality of independent executable tasks on the plurality of processing units. In addition, the device concurrently executes the plurality of independent executable tasks.