Build-Up Interconnect Structures Using Embedded Temporary Substrate
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Solution Overview
Problem
Semiconductor device manufacturing faces challenges in achieving smaller device sizes due to defects in build-up interconnect structures, particularly in larger packages with fine line spacing and multilayer structures, which are prone to warpage and contamination, and require costly laser drilling for vertical interconnections.
Innovation Solution
The use of an embedded temporary substrate with a low-cost, rigid material for forming top and bottom build-up interconnect structures over a carrier, which reduces warpage and eliminates the need for laser drilling by utilizing established silicon substrate fabrication methods, thereby minimizing manufacturing costs and increasing design flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If laser drilling is used to form vertical interconnections in build-up interconnect structures, then vertical connectivity is achieved, but manufacturing cost increases and manufacturing precision deteriorates due to warpage and contamination defects
Solution Approach 1:
The patent applies preliminary action by forming via holes through the build-up interconnect structure before depositing the conductive fill material. This preliminary via formation (through mechanical drilling or etching) eliminates the need for costly laser drilling during later stages, while the subsequent via fill process ensures reliable electrical connectivity. The preliminary structure preparation prevents warpage and contamination issues associated with laser drilling.
Solution Approach 2:
The patent replaces the laser drilling mechanism (optical/thermal system) with conventional mechanical drilling or etching methods to form via holes. This substitution eliminates the harmful thermal effects and contamination associated with laser drilling, reducing manufacturing cost while maintaining or improving interconnect structure reliability through more controlled via formation.
2Productivity
If build-up interconnect structures with fine line spacing and multilayer structures are used, then device integration is improved, but warpage and contamination defects increase
Solution Approach 1:
The patent segments the interconnect structure formation into distinct sequential steps: forming insulating layers, creating via holes, depositing conductive fill material, and planarizing surfaces. This segmentation allows each step to be optimized independently, enabling fine line spacing and multilayer structures to be formed with controlled warpage and contamination at each stage, thereby improving overall device integration while maintaining reliability.
Solution Approach 2:
The patent performs preliminary planarization and via formation steps before final conductive material deposition. These preliminary actions prepare the structure to accommodate fine line spacing and multilayer configurations without introducing warpage or contamination defects during subsequent processing, thus enabling high device integration density while maintaining interconnect reliability.
3Volume of moving object
If smaller semiconductor device sizes are achieved, then power consumption and footprint are reduced, but manufacturing precision deteriorates due to interconnect structure defects
Solution Approach 1:
The patent transitions from planar interconnect structures to three-dimensional build-up interconnect structures with multiple layers and vertical via connections. This dimensional evolution allows smaller semiconductor device footprints to achieve the required interconnect functionality through vertical stacking rather than lateral expansion, while the controlled via formation and fill processes maintain manufacturing precision even at reduced device sizes.
Data Source
AI summary
A semiconductor device has a first build-up interconnect structure formed over a substrate. The first build-up interconnect structure includes an insulating layer and conductive layer formed over the insulating layer. A vertical interconnect structure and semiconductor die are disposed over the first build-up interconnect structure. The semiconductor die, first build-up interconnect structure, and substrate are disposed over a carrier. An encapsulant is deposited over the semiconductor die, first build-up interconnect structure, and substrate. A second build-up interconnect structure is formed over the encapsulant. The second build-up interconnect structure electrically connects to the first build-up interconnect structure through the vertical interconnect structure. The substrate provides structural support and prevents warpage during formation of the first and second build-up interconnect structures. The substrate is removed after forming the second build-up interconnect structure. A portion of the insulating layer is removed exposing the conductive layer for electrical interconnect with subsequently stacked semiconductor devices.